Trouble with instantiation of RPM core - RLOCs are not obeyed


I have successfully made an RPM core using the floorplanner "Write RPM to UCF" feature and created a core.ngc and a core.ucf file. Before I created the core I applied the AREA_GROUP constraint to get a rectangular shape.

When I instantiate the core in another ISE project I can synthesize and implement without problems. However when I look at the placement of the design elements in floorplanner it looks nothing like what I saw when I made the core. Instead of a nice rectangular shape the core is now spread all over the FPGA! E.g. Two LUTs have RLOC values of X8Y13 and X23Y13 (delta_x,delta_y =

-15,0) are placed in X3Y115 and X46Y1 (delta_x,delta_y = -43,114)!

The core is fairly large and consists of about 1800 LUTs and 170 latches.

I have tried to to convert the the .ngc file to a .ndf file using the ngc2edif tool to check that the RLOCs are properly written to the core.ngc file and they seem to be.

When I created the core I did the following in ISE:

- Synthesis properties: remove "Add I/O buffers"

- Map Properties: remove "Trim Unconnected signals"

- Synthesize

- Implement->Translate

- Implement->Translate->Floorplan Design

- Assign AREA_GROUP contraint in floorplanner and write it to the ucf file.

- Run MAP and PAR.

- Implement->Place & Route->View/Edit Placed design.

- In floorplanner I select Floorplan->Replace all with placement

- I check that all elements in Design Hierarchy is placed on the floorplan.

- Select File->Write RPM to UCF

- Sets output UCF, input ngc, and output ngc file.

I'm using ISE 9.2.03i and a Virtex5 fpga.

What am I doing wrong?

Any help is appreciated.

Kind Regards Jon Neerup Lassen

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Jon Neerup Lassen
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