Regarding to necessary changes to verilog code, am I missing something,
- caches and memories, replacing using FPGA block rams.
- clock gating to clock enable
- change latches to registers Anything else?
What to look for when synthesising verilog code originally written for ASIC to FPGA?
Dec 08, 2007
1 Replies
That's a very broad question. What you need to do during the ASIC-
FPGA. For example, many (but not all) modern FPGAs include multiplier or MAC macros and fast adder chains. If your ASIC used multiply or add operations they may have been coded at the gate level which is wasteful if your FPGA has these built-in. In this case you'll want to abstract the arithmetic functions to allow inference of the native FPGA resources, or instantiate the primitives in your source code.
EB
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