Hi everyone,
I'm running Webpack ISE 9.2i (just updated to 9.2.04i/J40) on Suse10.1. This is not the 'blessed' RedHat but so far, this has worked great for compiling simple VHDL and putting it on a Spartan 3 kit.
I'd like to learn how to properly simulate my designs though, and I've tried to implement the 'Design Simulation' chapter from the ISE 9.2i Quickstart (which is actually the 9.1i quickstart):
However, trying to actually simulate the design returns "Simulator error
Parsing "counter_beh.prj": 0.02 Building counter_isim_beh.exe ERROR:Simulator:607 - ISE Simulator is unable to elaborate this design due to specific coding constructs used in the design. Xilinx is actively working on reducing the number of conditions where this error occurs. For more information on this error, please consult Answer Record 24067 in Answers Database at
I did of course look at the answer record in question, but none of the answers seem to apply to this case - one would assume that Xilinx's simple design isn't triggering such conditions anyway.
I've already googled a bit, and renamed the 'ld' commands in the Xilinx gcc subdirectories, but that didn't help. There are other Linux users with this same problem, but I've not found a solution so far.
Does anyone know how to get the simulation to work?
Otherwise - how can I run the simulation from the command-line so I can get a better idea of what it's trying to compile and where things are going wrong? One thing that I noticed is that it's apparently trying to create an .exe file, which wouldn't be suitable for a Linux platform.
Regards, Paul Boven.
P.S.: Yes, I'm aware that only RH is supported by Xilinx - but only Suse is supported by my employer :-)