Sythesisable subset of VHDL

The definitive answer is to follow the synthesis interoperability subse definded in IEEE 1076.6, but this is very restrictive, and you probabl cannot get hold of it without paying.

Altera, Xilinx, and Actel support very similar synthesisable subsets, s if you follow the XST guidelines you will not go far wrong. Inferrin RAMs, ROMs, and some other technology-related constructs is where thing may diverge. Being technology independent is a worthy aim, but gettin your design working on the technology you are using now is the primar goal.

This, unfortunately, isn't and easy question to answer in general. There are three classes of un-synthesizable code:

1. Constructs that make no sense for synthesis at all, such as delayed signal assignment or file I/O operations.
2. Constructs that are in theory synthesizable, but which in practice almost certainly aren't, for example transcendental floating point operations.
3. Constructs which should be synthesizable, but which aren't because of the limitations of the tools in use.

The grey area is number 3, but, luckily, these days tools are a lot better than they were a few years ago, and from experience there are very few items left in this class for most decent tools (including XST).

The simple answer is that if your synthesis tool accepts the code and meets area and timing requirements then your job is done.