Latest threads in Field-Programmable Gate Arrays

Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1

Hello all, I am writing to one of the software programmable registers (slv_reg0,1,2..) on a OPB slaves in the system us...

1 18yrs

narashimanc

1 18yrs narashimanc

Quicksim/modelsim

I am writing a testbench and one of the clock is a "gated clock" - meaning clock is clocking every time gate goes activ...

1 18yrs

martstev

1 18yrs martstev

ICAP attached to Microblaze on Virtex 2-pro..

Hi everybody, I'm trying to partially reconfigure my device (XC2VP30 on ML310 board) through ICAP. I have my ICAP attac...

6 18yrs

amirhossein.gholamipour

6 18yrs amirhossein.gholamipour

Why must a V4 be configured within 10 minutes of power up?

I was looking at the Virtex4 specs and notices a spec (Tconfig) that says you must configure within 10 minutes of apply...

5 18yrs

jcc

5 18yrs jcc

ANNC: ADC to FPGA Interface Webcast

Lattice is holding a webcast today, "Interfacing High Sample Rate ADCs to FPGAs." The presenter will be Shyam Chandra,...

5 18yrs

bart.borosky

5 18yrs bart.borosky

ASAP 2008 Submission deadline extended till 5th March'08

Dear Colleagues, Please accept our apologies if you receive multiple copies of this CFP. !!! DEADLINE EXTENDED !!! New...

0 18yrs

j4murali

0 18yrs j4murali

Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.

Hi, I have implemented a Microblaze v7.00.b with EDK 9.2 on a Virtex 4 fx12. A timer (xps_timer v1.00.a) generates an i...

6 18yrs

thomasrt2008

6 18yrs thomasrt2008

Tomorrow at Embeded in Nurnberg: Portable XSVF player demo

Hi I was not sure if i can get a working demo ready but it looks it I did: http://xiltendo.com it just shows a handheld...

0 18yrs

Antti.Lukats

0 18yrs Antti.Lukats

SPI indirect programming using spartan 3e

Will it be possible to use indirect programming of an SPI flash for Spartan 3E in future releases of ISE ? Im using 9.2...

3 18yrs

kislo02

3 18yrs kislo02

How to connect FPGA to a ASIC Board?

Hello Techies, I would like to use an off the shelf FPGA which I would be develpoing to test an ASIC or other FPGA. My...

8 18yrs

harisrini

8 18yrs harisrini

Viewing RTL schematic in Xilinx ISE

How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? I just upgraded from 8.2 because I couldn't fin...

2 18yrs

stef33d

2 18yrs stef33d

OPB_MDM as UART in a PowerPC design

Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to wo...

0 18yrs

pbantunez

0 18yrs pbantunez

Preventing optimization in cross clock domain logic

In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces...

6 18yrs

tom.derham

6 18yrs tom.derham

Convert some table into combinatorial circuit + optimization

Hi. Let's say, I have big table which is usually suitable to fit it in some ROM. But it's possible to construct some ci...

7 18yrs

drop669

7 18yrs drop669

ModelSim Natural arg value is negative

Hello Folks, Listed below is a simple NoBL SRAM model that I use to help me debug. Recently, I've been getting a ModelS...

3 18yrs

bradsmallridge

3 18yrs bradsmallridge

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