Field-Programmable Gate Arrays

ICAP attached to Microblaze on Virtex 2-pro..

Hi everybody, I'm trying to partially reconfigure my device (XC2VP30 on ML310 board) through ICAP. I have my ICAP attac...

6 comments posted 18yrs

posted by amirhossein.gholamipour

6 comments posted 18yrs posted by amirhossein.gholamipour

Why must a V4 be configured within 10 minutes of power up?

I was looking at the Virtex4 specs and notices a spec (Tconfig) that says you must configure within 10 minutes of apply...

5 comments posted 18yrs

posted by jcc

5 comments posted 18yrs posted by jcc

ANNC: ADC to FPGA Interface Webcast

Lattice is holding a webcast today, "Interfacing High Sample Rate ADCs to FPGAs." The presenter will be Shyam Chandra,...

5 comments posted 18yrs

posted by bart.borosky

5 comments posted 18yrs posted by bart.borosky

ASAP 2008 Submission deadline extended till 5th March'08

Dear Colleagues, Please accept our apologies if you receive multiple copies of this CFP. !!! DEADLINE EXTENDED !!! New...

0 comments posted 18yrs

posted by j4murali

0 comments posted 18yrs posted by j4murali

Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.

Hi, I have implemented a Microblaze v7.00.b with EDK 9.2 on a Virtex 4 fx12. A timer (xps_timer v1.00.a) generates an i...

6 comments posted 18yrs

posted by thomasrt2008

6 comments posted 18yrs posted by thomasrt2008

Tomorrow at Embeded in Nurnberg: Portable XSVF player demo

Hi I was not sure if i can get a working demo ready but it looks it I did: http://xiltendo.com it just shows a handheld...

0 comments posted 18yrs

posted by Antti.Lukats

0 comments posted 18yrs posted by Antti.Lukats

SPI indirect programming using spartan 3e

Will it be possible to use indirect programming of an SPI flash for Spartan 3E in future releases of ISE ? Im using 9.2...

3 comments posted 18yrs

posted by kislo02

3 comments posted 18yrs posted by kislo02

How to connect FPGA to a ASIC Board?

Hello Techies, I would like to use an off the shelf FPGA which I would be develpoing to test an ASIC or other FPGA. My...

8 comments posted 18yrs

posted by harisrini

8 comments posted 18yrs posted by harisrini

Viewing RTL schematic in Xilinx ISE

How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? I just upgraded from 8.2 because I couldn't fin...

2 comments posted 18yrs

posted by stef33d

2 comments posted 18yrs posted by stef33d

OPB_MDM as UART in a PowerPC design

Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to wo...

0 comments posted 18yrs

posted by pbantunez

0 comments posted 18yrs posted by pbantunez

Preventing optimization in cross clock domain logic

In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces...

6 comments posted 18yrs

posted by tom.derham

6 comments posted 18yrs posted by tom.derham

Convert some table into combinatorial circuit + optimization

Hi. Let's say, I have big table which is usually suitable to fit it in some ROM. But it's possible to construct some ci...

7 comments posted 18yrs

posted by drop669

7 comments posted 18yrs posted by drop669

ModelSim Natural arg value is negative

Hello Folks, Listed below is a simple NoBL SRAM model that I use to help me debug. Recently, I've been getting a ModelS...

3 comments posted 18yrs

posted by bradsmallridge

3 comments posted 18yrs posted by bradsmallridge

set_input_delay min and max (timequest)

Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface...

1 comments posted 18yrs

posted by Karel.Deprez

1 comments posted 18yrs posted by Karel.Deprez

Typical jitter of high frequency oscillators?

I'm looking for a "rule of thumb" of what I should expect in terms of jitter on the clock signal. It should be relative...

4 comments posted 18yrs

posted by ehliar-nospam

4 comments posted 18yrs posted by ehliar-nospam