In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces an output toggle (toggle_out) on the 2nd clock in response to a single-cycle pulse (pulse_in) on the 1st clock, using two processes and double buffering to mitigate metastability. In VHDL, it might look like this:
signal t1, t2, toggle : std_logic;
process(first_clk) begin if rising_edge(first_clk) if pulse_in = '1' then -- detect pulse on first_clk t1