Preventing optimization in cross clock domain logic

In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces an output toggle (toggle_out) on the 2nd clock in response to a single-cycle pulse (pulse_in) on the 1st clock, using two processes and double buffering to mitigate metastability. In VHDL, it might look like this:

signal t1, t2, toggle : std_logic;

process(first_clk) begin if rising_edge(first_clk) if pulse_in = '1' then -- detect pulse on first_clk t1

Reply to
Tom
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I can't say that I have thoroughly analyzed your code, but I think I can suggest some better code. It is only slightly different from yours, but I am sure it does not have any problems as it was given to me some years ago and has worked for myself and everyone else I know who has used it.

ClkDtctReg: process (RT, SysReset) begin if (SysReset ='1') then RTClkDetect

Reply to
rickman

Thanks very much for the code. I've interpreted it a bit for my case, which seems to work (using numeric_std):

signal t1, t2, t3 : std_logic;

----- process (in_clk_in, rst_in) -- on input clock begin if rst_in =3D '1' then t1

Reply to
Tom

I think you've got it. I don't see why you have the inner-most if statement conditioned on the XOR. That could be a simple assignment, if pulse_out

Reply to
rickman

TLDR

Hi Tom,

From the archive, Rick Collins once said --->

Anyone had big problems with similar async circuits? BTW, here is the simple sync circuit to generate a single pulse in the target clock domain regardless of the relative speed of the clocks.

|------- Metastable -------| __________ | | _____ |------O| inverter |-------|---------------| | Pulse | |__________| | | XOR |---->

| ______ ______ | ______ |--|_____| Out | | | | | | | | | |---| D Q |-----| D Q |--|--| D Q |--| Strobe | | | | | | /Clock | | | | | |

-------|> | ---|> | |---|> | |______| | |______| | |______| | | |___________|___________ Output Clock

The pulse out should be clean by the next clock edge as long as the routing is kept short. Or if the clock period is very short another FF can be added to feed the other leg of the XOR gate and assure a clean output. HTH, Syms.

Reply to
Symon

=A0 =A0 =A0 =A0 =A0_____

=A0 | XOR |---->

Out

=A0|

k

Thanks for that Symon -

checking the RTL schematic synthesized from my VHDL, the above seems to be what I've ended up with, albeit with extra registers on input and output, which are probably superfluous and just adding delay!

Best, Tom.

Reply to
Tom

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