Field-Programmable Gate Arrays

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System Verilog Import package error

Hello, I have a few packages that I have written like this: package A;
0 comments posted 7yrs
posted by nikhil777nix
0 comments posted 7yrs posted by nikhil777nix

What to do with an improved algorithm?

Hi, I think I've got a really good way to improve a commonly used & well establ ished algorithm that is often used in F...
19 comments posted 7yrs
posted by mikefield1969
19 comments posted 7yrs posted by mikefield1969

Re: Cheaptest FPGA board for Computer Architecture

> > > [1] Gnarly Grey UPDuino v1.0 Board $9.99 delivered > > 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, 8 Multipliers, 34 GPIO...
1 comments posted 7yrs
posted by jenfhaomndgfwutc
1 comments posted 7yrs posted by jenfhaomndgfwutc

PipelineC

Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should...
0 comments posted 7yrs
posted by absurdfatalism
0 comments posted 7yrs posted by absurdfatalism

8 bits vs. 9 bits in RAM Blocks

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some...
5 comments posted 8yrs
posted by gnuarm.deletethisbit
5 comments posted 8yrs posted by gnuarm.deletethisbit

Stepper motor controller

Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there...
2 comments posted 8yrs
posted by abirov
2 comments posted 8yrs posted by abirov

How to chnge this VHDL code into Verilog code

architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type...
1 comments posted 8yrs
posted by htizazu
1 comments posted 8yrs posted by htizazu

SPL2019 - Call For Papers

========================= ========================= ========== CALL FOR PAPERS IEEE - X Southern Conference on Programm...
0 comments posted 8yrs
posted by rodrigomelo9
0 comments posted 8yrs posted by rodrigomelo9

Searching for info about very old FPGA devices

Hello. My name is Rodrigo and I am from Argentina. I was looking for very o ld datasheets without success :-( (I search...
7 comments posted 8yrs
posted by rodrigomelo9
7 comments posted 8yrs posted by rodrigomelo9

Re: Very low pin count FPGA

> >> > Does any manufacturer make a very small programmable logic device >> > (with FLASH storage) is say a SOIC-8 or s...
5 comments posted 8yrs
posted by elson
5 comments posted 8yrs posted by elson

CAN Sniffer on Altera DE2-115 Board

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation boar d with the Terrasic AD/DA data co...
0 comments posted 8yrs
posted by denkedranjoe
0 comments posted 8yrs posted by denkedranjoe

CPLD 1.8V to 3.3V bidirectional SDA

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and leve...
10 comments posted 8yrs
posted by cydrollinger
10 comments posted 8yrs posted by cydrollinger