Field-Programmable Gate Arrays

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Chipscope

Hi! We are students working on implementing FFT on FPGA, virtex 4. We used Chipscope to test our code and capture signa...
5 comments posted 18yrs
posted by chithrakn
5 comments posted 18yrs posted by chithrakn

dual clock fifo

I wish to design a FIFO to tansfer data from a high speed clock domain(320 MHz) to low speed clock domain(40 Mhz). I do...
21 comments posted 18yrs
posted by FPGA.unknown
21 comments posted 18yrs posted by FPGA.unknown

EP2S130F1508C3N STRATIX II FPGA

Can anyone help me an Altera Stratix EP2S130F1508C3N? I need 500 pcs, but will take partials. Thanks in advance for taki...
0 comments posted 18yrs
posted by jon
0 comments posted 18yrs posted by jon

Xilinx Webcase Workflow

Austin, Peter, whoever: If someone dealing with a webcase finds that he is not the right person to deal with the case t...
7 comments posted 18yrs
posted by ksulimma
7 comments posted 18yrs posted by ksulimma

Designing CPU

Hi. It's probably not very good place for asking such, but there're should be at least those who knows starting points....
20 comments posted 18yrs
posted by climber.tim
20 comments posted 18yrs posted by climber.tim

implementing ethernet FCS code in verilog

hi, i am going to use easics tool for generating crc32 verilog code (8bit input) (www.easics.com/webtools/crctool) . i...
3 comments posted 18yrs
posted by dilan2005
3 comments posted 18yrs posted by dilan2005

Xilinx impact, boldly going into nightmareland

ISE 9.2SP4 blues again.. HDL synthesis passes only after anti-virus disable, ok learned that ISE is now in VIRUS catego...
1 comments posted 18yrs
posted by Antti.Lukats
1 comments posted 18yrs posted by Antti.Lukats

Need help in SDR

Good morning,my name is Emad i leave in egypt ,i taken BSC in communication & electronics engineering with GPA "A" an n...
2 comments posted 18yrs
posted by eng.emadsamuel
2 comments posted 18yrs posted by eng.emadsamuel

ISE 9.2SP4 error

ERROR:HDLParsers - Cannot reanme dependency database for library "work", file is "xst/work/hdpdeps.ref". Temporary data...
10 comments posted 18yrs
posted by Antti.Lukats
10 comments posted 18yrs posted by Antti.Lukats

ISSI SRAM.

Hi, I have a simple question about memory organization. I would like to write a memory controller for IS61LV25616AL SRA...
1 comments posted 18yrs
posted by gill81
1 comments posted 18yrs posted by gill81

Xilinx Tristate Registration

My tristate signals are not being placed in the IOBs. They are clocked signals, always all on or all off, depending on...
10 comments posted 18yrs
posted by bradsmallridge
10 comments posted 18yrs posted by bradsmallridge

Detecting a pulse with minimum width

I have an input signal that is required to be high for a certain length in time before a halt request is issued to a pr...
3 comments posted 18yrs
posted by mhs000
3 comments posted 18yrs posted by mhs000

Help on Virtex-II Pro global clocks.

Hi, I'm adding new logic to an existing IP. This IP uses a DCM to manage it's sys_clk. My logic is using another (exter...
7 comments posted 18yrs
posted by dteira
7 comments posted 18yrs posted by dteira