Designing CPU

A simple technique is to just implement the very basic instructions a cpu needs and then implement the rest as software functions. Instructions that you ought to have: Jump: Load instruction pointer from memory JumpSub: Push current instruction pointer on stack (stack++) Return: Load instruction pointer from stack (stack--) Move memory -> register Move register -> memory Compare register register and jump if equal Increase/Decrease register Shift left/right Add register + register -> register

This should give basic functionality for a performance penalty.

Have you looked at the obvious published options such as Picoblaze? It's tiny. Anything that looks like an ARM9 will NEVER be tiny.

Do you *need* 32-bit? What are you proposing to do with this slow CPU?

Take a look at the "light 8080" at open cores. The author made it very small. For fun I moved the registers into block RAM (M4K)and nearly halved the size down to 230 LE on Cyclone 2.

There is enough documentation with the project to get you started.

snipped-for-privacy@gmail.com wrote:

You do not need a left shift (add suffices) but the right shift is actually a necessary operation.

To the OP: Read fpgacpu.org (outdated but good)

Also see this:

Kolja Sulimma

Sounds like homework ?. If you want simple, search for MC14500, which will give you a very small opcode set, to start from. If this is targeting FPGA, then better might be Mico8, PicoBlaze, or similar 8 bit variants. Also, if size matters more than speed, you could look at a core optimised to execute from SPI Serial memory, and you could map spare, non-hardcoded opcodes, into a jump table - that allows you to make up more opcodes in firmware.

-jg

I would suggest you check out the 16C54 from Microchip, very simple instruction set and you can find a number of free implementations on the web in both Verilog/VHDL. I my experience writing the software tools take far more time than writing a simply processor so try to use an existing instruction set.

Good luck,

Hans

well, there are well-known candidates for SMALL FPGA CPU, but for the following spec

• 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC)
• serialized can run from spi flash up to 320MBit with
  formatting link
• can address large code space
• can run at high fabric clocks (due to lack of parallel buses and parallel ALUs)

now a bit-serialized CPU to the above spec can be done. it would use less than 100 slices.

if anyone is willing to desing this CPU, I may have funds for it, really please...

hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial flash!

so this serialized pico-cpu with less than 100 slices would outperform many

And as the same flash could be used for FPGA config this 10 MIPS engine comes virtually free.

pls do not suggest that picoblaze, or pic12 or i8080 can do this for this low fabric utilization

Anttis

His homework. ;)

Hi Antti, How many LUTs in a slice? In other words, what is your target usage in terms of 4-LUTs? Thanks, Syms.

Antti,

As you make a design more and more serial, you will often find yourself forced to add some extra registers. So a totally serial implementation is not necessarily the smallest one. In some of my own experiements, four bits proved to be the optimial size (though I was also taking performance into account when doing the evaluations).

-- Jecel

But in the Xilinx fabric, for instance, shift registers are very inexpensive. Antti's divider back on 22 Mar 2005 "divide by 2^n, n=3D21..37 =3D=3D> 3 Virtex Slices !!" was an excellent example of serial going very small.

Serial logic in FPGAs has some very strong advantages over parallel implementations for speed versus density metrics, allowing the fabric to often run at maximum FPGA clock speeds.

It's great stuff!

- John_H

Do you mean a 4 bit CPU, or a nibble-serial design of a larger

(There are 4 bit CPUs with tool chains, the Atmel MARC4, and the Atom from CoreRiver )

-jg

Did you mean you have someome to fund this, or that you could do it if someone funds you ?

and you can add a second SPI chip, if you want to double the bandwidth to 80MB/Sec. Of course, the jump latency does not improve, but a matched core design would minimise jumps. Short-Skip opcodes are an obvious cadidate.

-jg

In my case it was a nibble-serial implementation of a 16 bit processor. Antti is asking for large addresses, so the software should probably see 24 to 32 bits.

John_H wrote about shift registers in Xilinx FPGAs. I agree and have created some a really tiny design for a waveform generator using this. The problem I mentioned was that you need parallel addresses, however, and the shifts won't help you there. With a serial external memory you never need the whole address at once and might be able to avoid some registers. The instruction register might also have to be parallel, but by being smart when designing the instruction format you can avoid needing all the bits all the time.

-- Jecel

current funding...

Slow CPUs are usually also not very size efficient.

Maybe this is of interest, it recently found a new home:

Nice small instruction set, but maybe too limitd, because even implementing a shift operation (e.g. for implementing multiplication) would need multiple instructions. And 64 bytes of data/code memory doesn't look very useful.

Well, it obviously is not meant for real world applications.

This entire thread has been very interesting in how to "design and build" a CPU from an FPGA.

Even the subject line states this.

However, the OP of this thread was not looking for an education, he was looking for a complete project with little or no work on his part.

This is obvious by his posting from a gmail account.

Everyone who has added to this thread must have assumed that the OP was interested in the "design" of such a device.

I for one thank all those who added to this interesting discussion, I may have learned something myself.

donald