Field-Programmable Gate Arrays

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Detecting a pulse with minimum width

I have an input signal that is required to be high for a certain length in time before a halt request is issued to a pr...
3 comments posted 18yrs
posted by mhs000
3 comments posted 18yrs posted by mhs000

Help on Virtex-II Pro global clocks.

Hi, I'm adding new logic to an existing IP. This IP uses a DCM to manage it's sys_clk. My logic is using another (exter...
7 comments posted 18yrs
posted by dteira
7 comments posted 18yrs posted by dteira

Xilinx S3DSP + EDK Board, too good to be true?

Hi All, I was looking at the Xilinx website today and saw the new Spartan 3 DSP EDK board. It seems like a pretty good...
9 comments posted 18yrs
posted by joel.pigdon
9 comments posted 18yrs posted by joel.pigdon

DDR3 speed, Altera vs Xilinx

I get the impression that Altera is in the lead when it comes to speed on DDR[3] interfaces. Can anyone confirm/deny th...
26 comments posted 18yrs
posted by mleikvol
26 comments posted 18yrs posted by mleikvol

ICMP checksum

Does anyone know ICMP checksum calicutation by verilog HDL?
0 comments posted 18yrs
posted by life.is.dreaming
0 comments posted 18yrs posted by life.is.dreaming

Design entries for FSM

Does anyone know how can one enter FSM in Xilinx sysnthesis tool. I have a FSM in a text format called the kiss2 format...
8 comments posted 18yrs
posted by sudhangi
8 comments posted 18yrs posted by sudhangi

simulating Xilinx cores

I would like to simulate some modules in Verilog along with a FIFO generated by ISE core. I would like to know if it is...
1 comments posted 18yrs
posted by FPGA.unknown
1 comments posted 18yrs posted by FPGA.unknown

SDC of NCF?

Hey everyone, I recently started using Mentor Graphics Precision Synthesis for fpga's after Leonardo Spectrum stopped s...
2 comments posted 18yrs
posted by robquigley
2 comments posted 18yrs posted by robquigley

Problem with Spartan 3 StarterKit

Hello, ich have the Spartan3 StarterKit from Digilent. When I start the programming process in impact, all LEDs on the...
13 comments posted 18yrs
posted by webmaster
13 comments posted 18yrs posted by webmaster

ALTERA SOPC : ptf-sopc files

Hi all, SOPC version 7.1 and later use a new XML file format .sopc for storing system design data instead PTF format Fo...
1 comments posted 18yrs
posted by charles.wagner
1 comments posted 18yrs posted by charles.wagner

MAXDELAY="1.0"

I generate PCI-Express PHY with GTP wizard.the datawidth is selected 8bit or 16bit. but ,both the phy wrapper MAXDELAY...
0 comments posted 18yrs
posted by water9580
0 comments posted 18yrs posted by water9580

Almost offtopic about HDL optimizing.

Hi. I see how Quartus synthesizer removes unused parts of algorithm implemented in HDL, optimizes it and so on. Other s...
4 comments posted 18yrs
posted by drop669
4 comments posted 18yrs posted by drop669

Xilinx ISE Evaluation DVD 10.1 request...

Please, please, please fix the DVD installation-wizard, so that you can install the 32-bit (Webpack) tools on a 64-bit...
1 comments posted 18yrs
posted by anonymous
1 comments posted 18yrs posted by anonymous