Field-Programmable Gate Arrays

Raggedstone1 OEM Pricing now released.

We have now publically released the pricing for Raggedstone1 for OEM quantity pricing and for all those that keep askin...

0 comments posted 18yrs

posted by g1

0 comments posted 18yrs posted by g1

Viewing internal signals with ModelSim

Hi all, I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of t...

3 comments posted 18yrs

posted by jozamm

3 comments posted 18yrs posted by jozamm

problem testing the serial interface code from fpga4fun

I am testing the async_transmission module in xilinx webpack. But I couldn't see the waveform demonstrated in the tutor...

1 comments posted 18yrs

posted by fei.liu

1 comments posted 18yrs posted by fei.liu

Actel SX-A Timing Constraints Issues

Hello all, I helping a colleague debug a timing issue on his SX-A design. I don't have any experience with Actel device...

4 comments posted 18yrs

posted by kris.koorndyk

4 comments posted 18yrs posted by kris.koorndyk

chip scope

hi i have a question. i have an edk project that i want to debug. so i inserted a chipscope core. my question now is if...

3 comments posted 18yrs

posted by u_stadler

3 comments posted 18yrs posted by u_stadler

Spartan 3E intefacing for dummies

Hi all, just got Xylo-LM board (Spartan3E + FX2), I was searching for tips and tricks to avoid frying it. In particular...

14 comments posted 18yrs

posted by giuseppe.marullospamnot

14 comments posted 18yrs posted by giuseppe.marullospamnot

Synoplify ???

http://www.edn.com/article/CA6543758.html http://www.synplicity.com/corporate/pressreleases/2008/synopsys_acq.html Aaack...

11 comments posted 18yrs

posted by brimdavis

11 comments posted 18yrs posted by brimdavis

verilog question, break while loop to avoid combinational feedback during synthesis

Hello, I am puzzled by a statement in a book I am reading: To avoid combinational feedback during synthesis, a while lo...

4 comments posted 18yrs

posted by fei.liu

4 comments posted 18yrs posted by fei.liu

Modelsim XE III 6.x - huge fonts

I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it displays everything in HUGE fonts. On my 21" mon...

5 comments posted 18yrs

posted by vze24h5m

5 comments posted 18yrs posted by vze24h5m

Is there a means to conditional synthesis in VHDL?

Hi, I am designing a bunch (about 100) of short length tap (5 taps each) FIR. The tap coefficients would be many 1...31...

4 comments posted 18yrs

posted by rxjwg98

4 comments posted 18yrs posted by rxjwg98

timing and timing reports (again)

hi ich have question about timing. i have an edk design with microblaze (using spartan 3e 500) where i use an ip core t...

4 comments posted 18yrs

posted by u_stadler

4 comments posted 18yrs posted by u_stadler

Power Estimation of Microblaze (Power PC) based architectures

Hi I'm trying to estimate the power consumption of an architecture based on either Microblaze or PowerPC running a simp...

4 comments posted 18yrs

posted by ahosyney

4 comments posted 18yrs posted by ahosyney

PCI Express Configuration Testing

The Linux lspci -xxx command can show my PCIE device header space(0x00~0xFF). However,simultaneity,the Correctable Erro...

8 comments posted 18yrs

posted by water9580

8 comments posted 18yrs posted by water9580

Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?

Hi everyone, Just ordered a Spartan 3A ExtremeDSP Starter Kit. It comes without a programming cable, but I figured I co...

2 comments posted 18yrs

posted by boven

2 comments posted 18yrs posted by boven

Configure Spartan-3E w SD-Card?

I think someone here mentioned the possibility to configure an Xilinx Spartan-3E fpga with an SD-Card (MMC) in SPI mode...

7 comments posted 18yrs

posted by sky465nm

7 comments posted 18yrs posted by sky465nm