Field-Programmable Gate Arrays

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counterfeit Xilinx ?

I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese seller, and am having problems with random failures at fir...
27 comments posted 18yrs
posted by elson
27 comments posted 18yrs posted by elson

High speed memory read and transfer via rocket IO..

Hey, I want to read an 8bits data from a memory at 500MHz and want to send this serially at a speed of 4GBits/s. I am r...
6 comments posted 18yrs
posted by anilcelebi
6 comments posted 18yrs posted by anilcelebi

Raggedstone1 OEM Pricing now released.

We have now publically released the pricing for Raggedstone1 for OEM quantity pricing and for all those that keep askin...
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1

Viewing internal signals with ModelSim

Hi all, I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of t...
3 comments posted 18yrs
posted by jozamm
3 comments posted 18yrs posted by jozamm

Actel SX-A Timing Constraints Issues

Hello all, I helping a colleague debug a timing issue on his SX-A design. I don't have any experience with Actel device...
4 comments posted 18yrs
posted by kris.koorndyk
4 comments posted 18yrs posted by kris.koorndyk

chip scope

hi i have a question. i have an edk project that i want to debug. so i inserted a chipscope core. my question now is if...
3 comments posted 18yrs
posted by u_stadler
3 comments posted 18yrs posted by u_stadler

Spartan 3E intefacing for dummies

Hi all, just got Xylo-LM board (Spartan3E + FX2), I was searching for tips and tricks to avoid frying it. In particular...
14 comments posted 18yrs
posted by giuseppe.marullospamnot
14 comments posted 18yrs posted by giuseppe.marullospamnot

Synoplify ???

http://www.edn.com/article/CA6543758.html http://www.synplicity.com/corporate/pressreleases/2008/synopsys_acq.html Aaack...
11 comments posted 18yrs
posted by brimdavis
11 comments posted 18yrs posted by brimdavis

Modelsim XE III 6.x - huge fonts

I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it displays everything in HUGE fonts. On my 21" mon...
5 comments posted 18yrs
posted by vze24h5m
5 comments posted 18yrs posted by vze24h5m

timing and timing reports (again)

hi ich have question about timing. i have an edk design with microblaze (using spartan 3e 500) where i use an ip core t...
4 comments posted 18yrs
posted by u_stadler
4 comments posted 18yrs posted by u_stadler

PCI Express Configuration Testing

The Linux lspci -xxx command can show my PCIE device header space(0x00~0xFF). However,simultaneity,the Correctable Erro...
8 comments posted 18yrs
posted by water9580
8 comments posted 18yrs posted by water9580