Is there a means to conditional synthesis in VHDL?

You *can* do it with VHDL's if...generate construct. But it tends to get pretty clunky, and you may find that a C-based code generator is less painful.

VHDL is a ton better than Verilog for this, because you can freely use functions to manufacture the values of constants (based on other constants). Together with VHDL's wonderful unconstrained array mechanisms, you *should* be able to do what you need. But it won't be trivial, and testing it in all the possible combinations of cases will be a challenge.

If you're targetting an FPGA that has hardware multipliers, a likely better method is to write your code so that the multiply can be inferred and implemented using the hardware multiplier. It's higher performance, consumes no logic cells and is quicker and easier to write/debug/maintain. Take a look at the recommended coding styles for your intended targetted FPGA.

Kevin Jennings

Just run it through synthesis with the coefficients in as constants.

You'll be surprised (well, I was). When I had a long filter with small coefficients, I had to jump through hoops to get Synplify to use the hard multipliers instead of it being clever and doing shifts and adds!

Cheers, Martin

You can also use a case statement and hope that the compiler does not suck:

case factor is when 0: y