Synoplify ???

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Aaack, I'm having those awful FPGA Express flashbacks again....

Reply to
Brian Davis
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Oh dear God.

And here I was just talking with our great Synplicity reps today at our local Xtech. Things seemed okay with them - no news, no worries.

Say it ain't so, Joe...

- John_H

Reply to
John_H

I am not surprised, according to a 2005 Dataquest study 35% of ASIC designs are prototyped on FPGA's and I wouldn't be surprised if that number has doubled today. For this reason Mentor and Synplicity have spend a lot of R&D money to make ASIC netlist synthesis for FPGA's as easy as possible. In addition Synopsys gets the Hardi ASIC prototyping line. If you add to the mix the commoditisation of the lower/middle end of the synthesis market due to XST/QNS I wonder what direction Synopsys will take with Synplicity,

Hans

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Reply to
HT-Lab

My take on this:

- FPGA vendor tools (e.g. XST, Quartus) have improved to the extent that third party tools are no longer neccessary to get the most out of an FPGA. Synplicity is facing a shrinking market share if it sticks to the FPGA field.

- Synopsys finally gets a VHDL compiler that doesn't suck. This may be a good thing for the VHDL language. (Assuming that Synopsys isn't going to stop VHDL development in Synplify.)

Regards, Allan

Reply to
Allan Herriman

They would only continue development if there's a incentive to do so. Minimizing competition tend to decrease the will to make good customer offerings (with exception of a few out-of-the-box thinkers).

So are they too loose painfully if they screwup development? Is the management culture within Synopsys sound ..?

Reply to
sky465nm

Yes, having once tried quartus 1.0, I am still surprised that altera was able to catch up on language support and viewers. Synplicity was already focusing on asic prototyping as a result.

I expect that the FPGA tools will be left intact, but I would be pleasantly surprised if vhdl even shows up on the fpga to synopsys asic design roadmap.

-- Mike Treseler

Reply to
Mike Treseler

I remember about nine years ago having to debug a complex (for the time) VHDL-based FPGA design that a colleague had synthesized using the synthesizer built into Altera MaxPlus II. He had already complained about the numerous, and seemingly simple, VHDL constructs he couldn't use because the Altera VHDL implementation didn't support them. I decided to try using Leonardo Spectrum instead (or whatever it was called back then) and to my horror discovered that his VHDL contained a number of totally illegal constructs that the Altera synthesizer had managed to do something with without as much as a warning. It turned out to be one of these illegal constructs that was causing the design to fail.

Reply to
David Spencer

Is QII-1.0 the last version you tried?

I once was a Leonardo/Synopsys/Synplicity user. In the last few years both QII and XST have improved to the point where I see no point in maintaining the additional licenses. (Or the annoyance of a split tool chain.)

The last design I tried on both (A V2-1K, 75% full, 50MHz) Synplify Pro was 2 CLB's smaller and 5 Hz faster than XST.

$.02, G.

Reply to
ghelbig

Today I am using quartus 7.2. It works fine and has the best viewers.

We still have a leo license, but it is not used much. I agree that not having to deal directly with netlists and synthesis libraries is a plus for the designer. XST 9.1 has one vhdl synthesis bug that I have to work around, but it is usable for me.

Unfortunately for mentor, synplicity et. al. parity has been reached by some fpga vendors and vendor-independent synthesis licenses are much harder to justify than they once were.

-- Mike Treseler

Reply to
Mike Treseler

G., I guess the reason the two results go at the same speed is that the P&R tools don't optimise any further than the constraints specify. The performance of the synthesiser is truly revealed when timing is hard to meet. Possibly there is a similar argument to the CLB usage. The P&R tools spread the LUTs out over the all slices available. What was the difference in 4-LUT count? That's not to say that your implied point that XST is 'as good as' Synplify isn't true, it's just that the examples you provide to back up your position may not be appropriate. Cheers, Syms.

Reply to
Symon

The results are very design specific. I have seen in big timing critical designs that the vendor-independent tools make better end results in terms of density and clock frequency. Also the independent tools are usually much better in inferring complex structures (they tend to find memories in suprising places nowadays :))

Usually it's even hard to get designs that can be used with the two major independent tools trough the vendors tools (due to unsupported VHDL structures, not as good inferring etc.) So it is quite hard to test the vendor tools without major hacking of the code.

--Kim

Reply to
Kim Enkovaara

I have seen this also in one tight design. It is important to keep at least one vendor-independent synthesis license for this reason, and as check-off item for the design and the design rules.

However, if I can fit a standard design and make Fmax without tying up the fancy licenses, the group is better off.

It is possible to construct synchronous design rules that will pass the front ends of quartus, xst, mentor and synplicity. It's when I bend the rules with an asynch vendor element like a PLL or FIFO that testing is complicated. Sometimes the design can be structured into synchronous and asynchronous pieces.

-- Mike Treseler

Reply to
Mike Treseler

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