Field-Programmable Gate Arrays

SD-Card SDHC artificial 32GB limit

I just noticed one can get SDHC (SD-card 2.0) with 16 GB capacity for 89 EUR. The limit according to the v2.0 standard...

0 comments posted 18yrs

posted by sky465nm

0 comments posted 18yrs posted by sky465nm

Linux 2.6 PCI Device Driver on Virtex 4

I have spent the past few months slowly trying to get a PCI design with Linux 2.6 on the Virtex 4. I have been able to...

2 comments posted 18yrs

posted by bin.arthur

2 comments posted 18yrs posted by bin.arthur

Altera EPM7032S reading checksum

Hi, is it possible to read a checksum of a EPM7032S with Byteblaster an Max Plus II without having any information of h...

1 comments posted 18yrs

posted by maxitubo

1 comments posted 18yrs posted by maxitubo

DDR SDRAM interface for Virtex II Pro and Spartan3a

Hi I'd like to share with you my experience concerning DDR SDRAM interface development for XUP V2P baord, it may save y...

1 comments posted 18yrs

posted by robertwalczyk

1 comments posted 18yrs posted by robertwalczyk

ISE 10.0 finally with multi-threading and SV support ?

Will the 10th edition of ISE, to be relealed next week, finally support multithreading/SMP machines to reduce synthesis...

21 comments posted 18yrs

posted by heinerlitz

21 comments posted 18yrs posted by heinerlitz

A Challenge for serialized processor design and implementation

Hi I have been think and part time working towards a goal to make useable and useful serialized processor. The idea is...

64 comments posted 18yrs

posted by Antti.Lukats

64 comments posted 18yrs posted by Antti.Lukats

problem with edk9.2

Hi, I am trying to write values in to the slave registers through a c code.The problem here is that i am not getting a...

1 comments posted 18yrs

posted by jithinpremvas

1 comments posted 18yrs posted by jithinpremvas

Using TimeQuest Timing Analyzer

Hello, I'm trying to identify the critical path of a sequential circuit using the TimeQuest Timing Analyzer. However, I...

4 comments posted 18yrs

posted by gcorrea

4 comments posted 18yrs posted by gcorrea

Optimizing an inferred counter

Hello everyone, After banging our heads for last few weeks (sometimes literally), I figure I'll query the group of expe...

18 comments posted 18yrs

posted by martin.ryba.nospam

18 comments posted 18yrs posted by martin.ryba.nospam

serval PCIE issue

1>The Power Management Capability of PCIE can be removed? Is it option or necessary? My PCIE-based GbE controller repor...

1 comments posted 18yrs

posted by water9580

1 comments posted 18yrs posted by water9580

vhdl type conversions

hi can anybody help me out with my problem please: i have a custom type: type STATE_TYPE is (Idle, Read_Config, Read_Da...

10 comments posted 18yrs

posted by u_stadler

10 comments posted 18yrs posted by u_stadler

to view vhdl variable with gtkwave

Hello, When can i see vhdl variable with gtkwave. Currently i use three command inside cygwin: ghdl -a --ieee=synopsys...

3 comments posted 18yrs

posted by picnanard

3 comments posted 18yrs posted by picnanard

SGMII, xps_ll_temac and MDIO / MCD

Hi, I'm attempting to get the xps_ll_temac talking to an SGMII PHY (Vitesse 8211), with little success. The board doesn...

2 comments posted 18yrs

posted by jwilliams

2 comments posted 18yrs posted by jwilliams

FSL or DMA w/ FIFO?

Hello everyone, My project has several ADC channels with 16bit data up to 24kSPS. There is no need for each ADC sample...

7 comments posted 18yrs

posted by markmcmahon

7 comments posted 18yrs posted by markmcmahon

Xilinx interview questions

Hi, I have been called for a Xilinx internship (Computer / Electrical Engineering) interview. Could any of you please le...

4 comments posted 18yrs

posted by rkabhi

4 comments posted 18yrs posted by rkabhi