Synthesisable Timer in VHDL

hi all:

i am currently working on a "toy" design of my first big project (in VHDL) on the Xilinx Spartan III starter kit. now facing a timer problem and i could not properlly solve it using my limited design experience, here is it:

module A will prepare data for output (node : dout(7 downto 0)) to module B when it receive a READY signal from B. in order to notify B that the data is ready on the bus , A will ouput a signal DONE , but the DONE will be '1' after 30 ms A received signal READY and will just last 10 ms before going low. I wonder is there any standard or elegant way of implement the timer in VHDL?

PLZ give me some hint! thank U all in advance ! :)

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  1. Create constants of type time (or pass in as generics of type time) the clock period of your clock and the time period for your delays.
  2. Based on the value of those constants/generics compute the number of clocks that you would need to count (i.e. Max_count := Delay_Time / Clock_Period)
  3. Declare an integer signal in the range from 0 to Max_Count -1
  4. Create the code for a counter that counts from 0 to Max_Count - 1. When you get up to Max_Count - 1 your requested time interval has occurred so do whatever it is you want to do at that time.

Kevin Jennings

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When A receives the B's READY signal, A should place its data on the bus (dout), and then A should turn on a data-ready signal for B. When B has captured (latched) A's data, then B should turn off its READY signal. A will then turn off its data-ready signal.

There was a paper on the Xilinx website that dealt with this situation, but I think that Xilinx's method was faster/simpler than my "off the top of my head" method. HTH

-Dave Pollum

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Dave Pollum

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