i am currently working on a "toy" design of my first big project (in VHDL) on the Xilinx Spartan III starter kit. now facing a timer problem and i could not properlly solve it using my limited design experience, here is it:
module A will prepare data for output (node : dout(7 downto 0)) to module B when it receive a READY signal from B. in order to notify B that the data is ready on the bus , A will ouput a signal DONE , but the DONE will be '1' after 30 ms A received signal READY and will just last 10 ms before going low. I wonder is there any standard or elegant way of implement the timer in VHDL?
PLZ give me some hint! thank U all in advance ! :)