Field-Programmable Gate Arrays

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problem with uartlite in microblaze

Hi, I 'm learning to use microblaze (microblaze, EDK 9.1 sp2). I try to use the Send function of uartlite. Please, find...
0 comments posted 18yrs
posted by bhb22l
0 comments posted 18yrs posted by bhb22l

JavaBotics Marmaduke board

i need some detailed information about the Marmaduke board. JavaBotics website doesn't have enough information on some o...
0 comments posted 18yrs
posted by ghori.asad
0 comments posted 18yrs posted by ghori.asad

PCI Express Switch

Hi We are currently looking for switch solution based on PCI express to connect several Xilinx FPGA boards together. It...
0 comments posted 18yrs
posted by shakith.fernando
0 comments posted 18yrs posted by shakith.fernando

CAM implementation using Dual port ram

Hi, I am going through a xilinx app note. The basic CAM that is shown is a 32X9 capacity. The total memory capacity use...
1 comments posted 18yrs
posted by sharan.basappa
1 comments posted 18yrs posted by sharan.basappa

FPGA board with an ADC

Hi, I am looking for an FPGA board with preferably a Xilinx FPGA (Spartan 3 or Virtex series) with 500k to 1 million ga...
0 comments posted 18yrs
posted by sheikh.m.farhan
0 comments posted 18yrs posted by sheikh.m.farhan

Dual Independent Aurora Links on One GTP Tile

Hi all, Hope to get some guidance here. Target device is the Virtex-5 SX50T on the ML506 eval board. I'm trying to buil...
0 comments posted 18yrs
posted by scott.yuan523
0 comments posted 18yrs posted by scott.yuan523

zpu processor core

hi, Did anybody give the new "zpu" core a try located at opencores.org? In a way it's an attractive core with a 32 bits...
0 comments posted 18yrs
posted by blop
0 comments posted 18yrs posted by blop

Xilinx ISE 9.2i out of memory

Hi, ISE reports an out of memory error while synthesizing a design which has 10,000 instantiations of a simple verilog...
3 comments posted 18yrs
posted by ashwinihs
3 comments posted 18yrs posted by ashwinihs

ddr2 controller for xilinx 1800a dsp starter kit

Hi xilinx geeks, mig2.1 can generate a ddr2 controller only for 3400adsp starter kit. is there a fully tested design su...
0 comments posted 18yrs
posted by rponsard
0 comments posted 18yrs posted by rponsard

Simulink(Matlab)/FPGA serial communication

Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto...
3 comments posted 18yrs
posted by sarah.stregel
3 comments posted 18yrs posted by sarah.stregel

Simulink(matlab)/FPGA serial port communication

Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto...
1 comments posted 18yrs
posted by sarah.stregel
1 comments posted 18yrs posted by sarah.stregel