Writing to DDR RAM on Virtex II Pro Board on PLB Bus

My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus?

Background: I am developing a custom IP core for a Virtex II Pro based system (the Xilinx XUP board). This core captures video data using the Digilent VDEC1 board at a pixel rate of 13 MHz. I would like to write several video frames to memory and process them in the Power PC processor.

Right now my core captures video and attempts to send it to the PPC using the PLB FIFO IPIF. However, there are several problems with this approach. It turns out that reading this data from the FIFO in software is extremely slow, so the FIFO fills up before I can read all of the pixels out of it (resulting in lost pixels and unusable frames). Also, there is only enough memory in the FIFO to store about one image frame (360x240 resolution), so it could not serve as a multi- frame buffer (and I need about 8 frames to do my processing)

Therefore, I would like to write the image data directly to DDR SDRAM from my custom IP core. I have 512 MB installed on the board, and I'm able to access it in C using the plb_ddr core. However, I am not sure how I can get my custom core to write to the DDR using the PLB bus.

If anyone could point me in the right direction, I would really appreciate it. I know that I will need to make my custom core a "Master" on the PLB bus and possibly use DMA, but I can't find a good example on how to read/write to memory.


Reply to
Loading thread data ...

From my experience, I'll tell you that I have used open_ddr core from opencores to use with PowerPC. It is not easy but possible. In your case I will use plb_ddr core. I would do this:

- First of all, I'd generate the design with the EDK including DDR memory.

- Second I'd use ISE to edit the system internal connection, so I'd disconnect DDR from PPC and connect to my custom core. Only You have to study the signal provided by PLB_IPIF to know what to do.

This is my opinion. I hope it could help you.

Reply to

There are a couple of choices you have when it comes to writing back to external memory from your core. Depending on which versions of the tools you are using you can do a pretty simple DMA from your core (across the PLB) or directly connect your core to external memory (say, via the MPMC). I tend to lean towards the MPMC as it is a much higher bandwidth solution than the PLB, but it is a little more complex. If you are using >=9.2i tools there is a good Answer Record on Xilinx's website about using the Native Port Interface (NPI) with the Multi-Ported Memory Controller.

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.