Field-Programmable Gate Arrays

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One more question. WebPACK key with ISE

One more question. For example, I have no WebPACK distributive but I have ISE Foundation distributive. May I use ISE Fo...
1 comments posted 18yrs
posted by zlyhan
1 comments posted 18yrs posted by zlyhan

loop back on a MARVELL switch

Hi all, I have a marvell switched based system with two ports. I want to loop back packets that i send on this switch. C...
0 comments posted 18yrs
posted by ramaarchana
0 comments posted 18yrs posted by ramaarchana

Downloading some data from flash memory thru JTAG.

Hi. I have common configuration scheme for Altera Stratix II: flash memory + Max device + Stratix II. Flash memory conf...
0 comments posted 18yrs
posted by climber.tim
0 comments posted 18yrs posted by climber.tim

problem with synthesis

The following module generates this error: The logic for does not match a known FF or Latch template. The logic for doe...
1 comments posted 18yrs
posted by fei.liu
1 comments posted 18yrs posted by fei.liu

synplify pro generates negative slack

SRLen7 : SRL16 -- synthesis translate_off generic map( INIT => x"0000") -- synthesis translate_on port map (Q => enadd5...
5 comments posted 18yrs
posted by nbg2006
5 comments posted 18yrs posted by nbg2006

No synchronization word in prom file (XILINX)?

I tried to reflash my SPI FLASH memory with the DOS program supplied by XILINX (I don't remember the name of the DOS pr...
2 comments posted 18yrs
posted by bubba
2 comments posted 18yrs posted by bubba

Beginner's silly question about ICAP

Hi Comrade, I run into troubles trying to read anything using ICAP. I set "-g security:none", just in case. When I try...
3 comments posted 18yrs
posted by g.drozdzowski
3 comments posted 18yrs posted by g.drozdzowski

EDK 10.1 first impressions

Hi here it goes: I got last week new notebook that is faster then the desktop, so I installed 10.x tools there. And I h...
6 comments posted 18yrs
posted by Antti.Lukats
6 comments posted 18yrs posted by Antti.Lukats

Conterfeit parts guidance

Hello all, I am a Quality manager at Xilinx, and I have asked to provide specific guidance on the question of counterfi...
9 comments posted 18yrs
posted by craig.taylor
9 comments posted 18yrs posted by craig.taylor

Xst_Choice nodes

Hey, Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting this error ERROR:Xst:2259 - Unit has internal...
1 comments posted 18yrs
posted by robquigley
1 comments posted 18yrs posted by robquigley

"Number of BSCANs: 2 out of 1 200%"

Hi, I have added Chipscope to my design, but it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of...
6 comments posted 18yrs
posted by pbantunez
6 comments posted 18yrs posted by pbantunez