Xilinx FPGA + SMPS

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Is there any known pitfalls or problems with driving xilinx fpga (spartan)
with smps (buck) ..?

Re: Xilinx FPGA + SMPS
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Yes, not reading the "Troubleshooting hints" section of AN19 first.
Particularly hint 12.
Google :-
AN19 site:linear.com

HTH., Syms.

Re: Xilinx FPGA + SMPS
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Re: Xilinx FPGA + SMPS

Go here:

http://www.xilinx.com/products/design_resources/power_central /

Then scroll down to the manufacturers.

Pick the one you like, and go to their Xilinx FPGA power supply pages.

All choices are "approved" for use with ALL Xilinx product.

We (I personally) spend a lot of time with these folks, to ensure a
smooth (pun intended) powering experience.

Not sure why the other negative posts...perhaps these are the folks who
ignore our hard work, and decide to see if a power solution works all on
their own.


Re: Xilinx FPGA + SMPS

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Perhaps a lot of designers are not happy with the fact they are
treated as complete idiots when it comes to SMPS design :-)

Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Re: Xilinx FPGA + SMPS

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  I'd be less worried about SMPS design, and more worried about the
undocumented interaction of things like fold-back and StartUp
current peaks.
  It's what they DONT say that matters, and there is a lot to be said for
a design that has been tested (and one hopes, fully margined by Austin!)


Re: Xilinx FPGA + SMPS
On Sat, 05 Apr 2008 11:48:43 +1200, Jim Granville

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Sometimes the app notes and datasheets are wrong as well.  For
example, I've seen plenty of DC/DC converter module datasheets that
indicate that adding more low-ESR capacitance on the output of a DC/DC
converter module will improve transient response.

A closer look reveals that the app note or datasheet was written
around the turn of the century, before modern large ceramic or organic
polymer electrolytic caps became commonly available.  These have much
lower ESR than the app note authors anticipated, and are capable of
making older DC/DC converter modules oscillate, or at least exhibit
poor transient response.

This isn't a problem if you design your own DC/DC converter (in which
case you can tune the compensation network to suit the load) or a more
modern module with a compensation network designed for a large
capacitive load.

This pdf gives more information:
http://www-03.ibm.com/procurement/proweb.nsf/objectdocswebview/file15+-+ibm+06+capacitance+and+transient /$file/15+-+ibm+06+capacitance+and+transient+06_08_18.pdf


Re: Xilinx FPGA + SMPS

That is why our power partners read my app notes, and wee read their
appnotes, and every Xilinx circuit app note must be built and tested (if
it is hardware, it has to have a pcb...).


Re: Xilinx FPGA + SMPS

My hat is off to you if know how to calculate Ldi/dt, and determine the
gap in the ferrite inductor, but yes, if we are talking in VHDL/verilog,
which we do 99.999% of the time, then the people require a power supply
solution, canned, and ready to go.


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