Field-Programmable Gate Arrays

Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully sy...

2 comments posted 18yrs

posted by mansoor.naseer

2 comments posted 18yrs posted by mansoor.naseer

why to trigger a NMI error after just receiving 35 pakcets?

My PCIE device is a Gigabit NIC. The lnx ifconfig command can show the tx/rx packet count from this NIC. after loading...

1 comments posted 18yrs

posted by water9580

1 comments posted 18yrs posted by water9580

You M.ust know this to get Financial Aid!

The steps of the financial aid application process are: 1. A student applies for admission before the admission applica...

0 comments posted 18yrs

posted by DownloadTVepisodesejda

0 comments posted 18yrs posted by DownloadTVepisodesejda

clock instanciation

Hi, in my book it's written that the clock has to instactiated like this : architecture Behavioral of fftest is constant...

4 comments posted 18yrs

posted by webmaster

4 comments posted 18yrs posted by webmaster

Specifying strict setup constraint in ISE

Hi All, I need to specify the strict setup time for the group of signals. It can be relatively high, but I need very lo...

4 comments posted 18yrs

posted by wzab

4 comments posted 18yrs posted by wzab

Xilinx FFT C-sim model

I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am work...

2 comments posted 18yrs

posted by petersen.curt

2 comments posted 18yrs posted by petersen.curt

Xilinx CPLD programming tool under Linux

Hi all ! I'm wondering if a basic tool already exist to program Xilinx CPLD (XC95144 and so) under Linux (preferably wit...

7 comments posted 18yrs

posted by habib

7 comments posted 18yrs posted by habib

Task in verilog

Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl. Verilog => // string...

2 comments posted 18yrs

posted by FPGA.unknown

2 comments posted 18yrs posted by FPGA.unknown

looking for critique for a spartan3a lcd controller verilog module

Hello gentle readers, I started playing with FPGA and verilog about a month ago. As a fun starting project, my goal is...

1 comments posted 18yrs

posted by fei.liu

1 comments posted 18yrs posted by fei.liu

Disable optimisation - Ring oscillator

Hello, I have a project where i have to implement a ring oscillator (3 not gates) using an altera DE2. But i am confron...

7 comments posted 18yrs

posted by franck110

7 comments posted 18yrs posted by franck110

32 bit multiplier

Hi All This application I am looking at requires 17 tera bytes of multiplication per second. Which in an FPGA means 40K...

9 comments posted 18yrs

posted by thevipulsinha

9 comments posted 18yrs posted by thevipulsinha

Starting a PCI Express Application

Hello, I need a PCI Express application and I could find a vendor that sells PCI Express cards and add in my design to...

2 comments posted 18yrs

posted by jjlindula

2 comments posted 18yrs posted by jjlindula

Intel plans to tackle cosmic ray threat

Dear All, Austin in particular, I saw this and thought of you! Cheers, Syms. http://news.bbc.co.uk/1/hi/technology/73353...

24 comments posted 18yrs

posted by symon_brewer

24 comments posted 18yrs posted by symon_brewer

NoisII or else.

Hi, Simple question. Can I put a NiosII on an FPGA alone, no ROM no DRAM no SRAM no nothing, Just the FPGA ? (examples...

8 comments posted 18yrs

posted by cupidoREMOVE

8 comments posted 18yrs posted by cupidoREMOVE

OBUF gate delay

Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle f...

3 comments posted 18yrs

posted by jamicrotech

3 comments posted 18yrs posted by jamicrotech