Latest threads in Field-Programmable Gate Arrays

Split register in smaller segments

Hi, I'm working on a little UART to get more familiar with verilog, and right now I have the following input: parameter...

5 18yrs

mickeymeeuw

5 18yrs mickeymeeuw

Xilinx ISE synthesis error (error:3524 Unexpected end of line.)

Hello, when trying to synthesize a VHDL file (part of a design) that has already been compiled and simulated by Modelsi...

0 18yrs

giorgos.puiklis

0 18yrs giorgos.puiklis

Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully sy...

2 18yrs

mansoor.naseer

2 18yrs mansoor.naseer

why to trigger a NMI error after just receiving 35 pakcets?

My PCIE device is a Gigabit NIC. The lnx ifconfig command can show the tx/rx packet count from this NIC. after loading...

1 18yrs

water9580

1 18yrs water9580

You M.ust know this to get Financial Aid!

The steps of the financial aid application process are: 1. A student applies for admission before the admission applica...

0 18yrs

DownloadTVepisodesejda

0 18yrs DownloadTVepisodesejda

clock instanciation

Hi, in my book it's written that the clock has to instactiated like this : architecture Behavioral of fftest is constant...

4 18yrs

webmaster

4 18yrs webmaster

Specifying strict setup constraint in ISE

Hi All, I need to specify the strict setup time for the group of signals. It can be relatively high, but I need very lo...

4 18yrs

wzab

4 18yrs wzab

Xilinx FFT C-sim model

I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am work...

2 18yrs

petersen.curt

2 18yrs petersen.curt

Xilinx CPLD programming tool under Linux

Hi all ! I'm wondering if a basic tool already exist to program Xilinx CPLD (XC95144 and so) under Linux (preferably wit...

7 18yrs

habib

7 18yrs habib

Task in verilog

Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl. Verilog => // string...

2 18yrs

FPGA.unknown

2 18yrs FPGA.unknown

looking for critique for a spartan3a lcd controller verilog module

Hello gentle readers, I started playing with FPGA and verilog about a month ago. As a fun starting project, my goal is...

1 18yrs

fei.liu

1 18yrs fei.liu

Disable optimisation - Ring oscillator

Hello, I have a project where i have to implement a ring oscillator (3 not gates) using an altera DE2. But i am confron...

7 18yrs

franck110

7 18yrs franck110

32 bit multiplier

Hi All This application I am looking at requires 17 tera bytes of multiplication per second. Which in an FPGA means 40K...

9 18yrs

thevipulsinha

9 18yrs thevipulsinha

Starting a PCI Express Application

Hello, I need a PCI Express application and I could find a vendor that sells PCI Express cards and add in my design to...

2 18yrs

jjlindula

2 18yrs jjlindula

Intel plans to tackle cosmic ray threat

Dear All, Austin in particular, I saw this and thought of you! Cheers, Syms. http://news.bbc.co.uk/1/hi/technology/73353...

24 18yrs

symon_brewer

24 18yrs symon_brewer

Field-Programmable Gate Arrays

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