32 bit multiplier

Assuming that you mean 17 10^12 multipliers?

With a 90nm process you can get quite a few in a standard cell ASIC. But without further explanation, I would say that speed per multiplier will be dreadfull: you won't be able to get that much data on and off a single chip (I/O limitations). So you may stick to an FPGA as well (saves you time and risk, read on).

As for your FPGA count: you need 3 DSP48 blocks on a Xilinx device or 1

But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are more than 100 of these in the larger V5 SX(T) devices (too lasy to look up the exact number), you will end up with quite a bit less than 1000 FPGAs.

Still, you need to look at your I/O, power, algorithm, costs, etc. to get the whole picture.

Regards, Alvin.

Approx 1000 in the SX240, so approx 100 FPGAs. A big project!

Perhaps use the money it costs for all those FPGAs to pay off someone who already knows the encryption key? Just a thought, Syms.

But not totally outrageous. I've recently completed a beamforming antenna design for installation in an aircraft that uses one Virtex

Aren't you supposed to shoot everybody you tell about the project?

GAs.

stadt.de

Slightly off-topic: Here is a civilian research application at CERN, where 120 Virtex 4FX devices "digest" and pre-process a thousand data streams of 2.5 Gbps each. I was peripherally involved, and I helped write the press release...

Why ? I'm sure this is for a crop-duster, right ? ;)

-jg

You could also do the calculations for :

-jg

release...

So that's why Volker Lindenstruth is hosting the FPL this year. I worked on something like the predecessor of that beast in 1995. Processing 100.000 data streams at 10MHz.

Kolja Sulimma