Specifying strict setup constraint in ISE

There is no way any FPGA (or other IC) can guarantee a combinatorial plus routing delay to be 5 ns min, 6 ns max. Just normal ambient temperature and Vcc variations exceed these tolerances, You may perhaps be able to make the delays track (which is what you seem to be after) but absolute delay precision is out of the question, Now, if you register these values in a register driven by a global clock, the Qs may have very little delta delay, BTW, in my book, "set-up time" is a timing requirement on the D-input of a register or flip-flop, never a physical delay. Maybe that's the difference between the two manufacturers... Peter Alfke, Xilinx

When signals are absolutely critical to be low skew as in oversampling or otherwise very high speed designs, I and many others resort to using manual placement and often constrained routes. If the routing is regular, often one constrained route can cover a multitude of signals.

Constrained routing is an advanced feature that requires some work inside FPGA Editor to generate the constraints. Solid knowledge of the physical workings around the IOBs and signal routing boxes helps significantly. Much of that knowledge comes from "poking around" inside the chip trying different routes both automated and manual.

There are some application notes on wide, very high speed buses that use the physical constraints to tie down how things behave coming into the chip. How precise you get depends on how extreme your design goals are.

- John_H

If you can generate the required phase relationship with your clock signal (to the sampling flip-flops) instead of playing with the input delay to the flop D, it is fairly simple to have a low skew sampling when you use the IOB flip-flops. Then the only routing that comes into play is the clock, and this can be adjusted using DCM resources. This assumes you don't insert the delay element in each IOB between the pin and the D. Newer Virtex parts also have variable input delay elements that can help to remove residual skew, but for a 1 ns window this should not be necessary.

Good advice. May I also recommend some reading for the OP?

directed routing site:xilinx.com

HTH., Syms.