Hi, in my book it's written that the clock has to instactiated like this :
architecture Behavioral of fftest is constant T : time := 20ns; ... begin ... --clock process begin clk
clock instanciation
Apr 10, 2008
4 Replies
Hi Thorsten, Your book is talking about simulation. You can't synthesise that code, because the FPGA can't implement delays like that. You need an external clock for synthesis that connects to your design through an input port. HTH., Syms.
OK, I found the pin, now another question. This is also for simulation only: reset
No synthesis code is required for reset or clock other than the input port declarations. Some testbench process can wiggle it however you like.
-- Mike Treseler
generate_reset : process begin reset
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