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clock instanciation

Hi, in my book it's written that the clock has to instactiated like this :

architecture Behavioral of fftest is constant T : time := 20ns; ... begin ... --clock process begin clk

Reply to
Thorsten Kiefer
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Hi Thorsten, Your book is talking about simulation. You can't synthesise that code, because the FPGA can't implement delays like that. You need an external clock for synthesis that connects to your design through an input port. HTH., Syms.

Reply to
Symon

OK, I found the pin, now another question. This is also for simulation only: reset

Reply to
Thorsten Kiefer

No synthesis code is required for reset or clock other than the input port declarations. Some testbench process can wiggle it however you like.

-- Mike Treseler

Reply to
Mike Treseler

generate_reset : process begin reset

Reply to
Symon

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