Hello gentle readers,
I started playing with FPGA and verilog about a month ago. As a fun starting project, my goal is to allow interaction between host linux pc and fpga lcd display. The connection is made through serial RS323 interface. Here is my lcd controller module that accomplished my goal. I am looking for your advice and suggestions and in what ways I can improve this module. I am hoping to learn from this process. There are some line folding problems during copy/paste, I tried my best to fix them. There are some code snippets I copied from other modules as you can see distinctively different styles of variable naming. I should fix these style issues. (ise don't play well with vim //sigh).
module lcd_controller (clk, data_ready, rx_data, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
parameter k = 18; parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while // the character is been transmitted parameter clr = 8'h0A;
input clk; // synthesis attribute PERIOD clk "50 MHz" input data_ready; input [7:0] rx_data; output lcd_rs; output lcd_rw; output lcd_e; output lcd_7; output lcd_6; output lcd_5; output lcd_4;
reg lcd_e, lcd_rs, lcd_rw, lcd_7, lcd_6, lcd_5, lcd_4;
reg [k+8:0] count=0; reg [6:0] lcd_code = 0;
reg [2:0] state=3'b000; reg [2:0] next_state=3'b000;
wire lcd_ready = (state==1);
// store rx_data locally reg [7:0] lcd_dataReg; always @(posedge clk) if(data_ready & lcd_ready) lcd_dataReg