Latest threads in Field-Programmable Gate Arrays

Anyone have files from the old Xilinx FTP?

Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the file...

5 7yrs

timbuck2

5 7yrs timbuck2

Cyclone V decimation

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be...

14 7yrs

peter.pan

14 7yrs peter.pan

MachXO2 internal clock tolerance / accuracy

Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to...

1 7yrs

yvo.zoer

1 7yrs yvo.zoer

Testing (please ignore)

Please ignore

0 7yrs

aprichelieu

0 7yrs aprichelieu

Is it possible to implement Ethernet on bare metal FPGA, Without Use of any Hard or Soft core processor?

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be do...

49 7yrs

swapnilpatil27497

49 7yrs swapnilpatil27497

Open Source Synthesis Tools

I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simu...

3 7yrs

gnuarm.deletethisbit

3 7yrs gnuarm.deletethisbit

Xilinx Artix-7 SoM with 8 x GTPs

Hello, I'm looking for a Xilinx Artix-7 SoM (or board..) with at-least 8 x GTP transceivers , preferably 16 , exposed to...

1 7yrs

rotem.gazit

1 7yrs rotem.gazit

ARM + FPGA CPU Module running Yocto Linux?

Is there any ARM + FPGA CPU Module running linux using any of: * NXP i.MX6/7/... * Texas Instrument Sitara AM335x or be...

32 7yrs

aprichelieu

32 7yrs aprichelieu

Altera Cyclone replacement

Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on...

36 7yrs

stef33d

36 7yrs stef33d

Need help to understand: Efficient Multi-Ported Memories for FPGAs

Hi, I cannot understand the following paper: "Efficient Multi-Ported Memories for FPGAs" http://www.eecg.toronto.edu/~s...

26 7yrs

wtxwtx

26 7yrs wtxwtx

initializing a small array in Verilog

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem...

3 7yrs

dab

3 7yrs dab

Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Hi, Can I use Verilog or SystemVerilog to write a state machine with clock gating function? I know VHDL has no such fun...

68 7yrs

wtxwtx

68 7yrs wtxwtx

Merry Christmas / Happy Holidays

To all: May your year finish well, and your 2019 be even brighter. Merry Christmas / Happy Holidays to all who celebrate...

4 7yrs

rick.c.hodgin

4 7yrs rick.c.hodgin

What is the name of the circuit structure that generates a state machine's jumping signals?

Hi, What is the name of the circuit structure that generates a state machine's jumping signals? I remember I looked at...

45 7yrs

wtxwtx

45 7yrs wtxwtx

Help with Pmod VGA on Altera

I have a Cyclone V GX Starter kit board, with Quartus 13.1: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language...

5 7yrs

rick.c.hodgin

5 7yrs rick.c.hodgin

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