Field-Programmable Gate Arrays

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Cyclone V decimation

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be...
14 comments posted 7yrs
posted by peter.pan
14 comments posted 7yrs posted by peter.pan

MachXO2 internal clock tolerance / accuracy

Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to...
1 comments posted 7yrs
posted by yvo.zoer
1 comments posted 7yrs posted by yvo.zoer

Testing (please ignore)

Please ignore
0 comments posted 7yrs
posted by aprichelieu
0 comments posted 7yrs posted by aprichelieu

Open Source Synthesis Tools

I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simu...
3 comments posted 7yrs
posted by gnuarm.deletethisbit
3 comments posted 7yrs posted by gnuarm.deletethisbit

Xilinx Artix-7 SoM with 8 x GTPs

Hello, I'm looking for a Xilinx Artix-7 SoM (or board..) with at-least 8 x GTP transceivers , preferably 16 , exposed to...
1 comments posted 7yrs
posted by rotem.gazit
1 comments posted 7yrs posted by rotem.gazit

ARM + FPGA CPU Module running Yocto Linux?

Is there any ARM + FPGA CPU Module running linux using any of: * NXP i.MX6/7/... * Texas Instrument Sitara AM335x or be...
32 comments posted 7yrs
posted by aprichelieu
32 comments posted 7yrs posted by aprichelieu

Altera Cyclone replacement

Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on...
36 comments posted 7yrs
posted by stef33d
36 comments posted 7yrs posted by stef33d

initializing a small array in Verilog

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem...
3 comments posted 7yrs
posted by dab
3 comments posted 7yrs posted by dab

Merry Christmas / Happy Holidays

To all: May your year finish well, and your 2019 be even brighter. Merry Christmas / Happy Holidays to all who celebrate...
4 comments posted 7yrs
posted by rick.c.hodgin
4 comments posted 7yrs posted by rick.c.hodgin

Help with Pmod VGA on Altera

I have a Cyclone V GX Starter kit board, with Quartus 13.1: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language...
5 comments posted 7yrs
posted by rick.c.hodgin
5 comments posted 7yrs posted by rick.c.hodgin

Estimating ROM gate count in ASIC

I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estima...
12 comments posted 7yrs
posted by kevin.neilson
12 comments posted 7yrs posted by kevin.neilson