3 years ago
I cannot understand the following paper:
"Efficient Multi-Ported Memories for FPGAs"
FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
The paper essence for 2 write ports and 2 read ports is:
There are 2 memory blocks each having 1 write port and 2 read ports.
The 2 memory blocks provide 2 write ports to write independently.
There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
Write through port 1 with address 3; --- no problem
Write through port 0 with address 2;
0 --> LVT(2);
1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.