I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any case.
I'm pretty sure there is an open source tool for backend place and route and bit stream generation of the Lattice iCE40 devices, well, some of them anyway. I don't recall what they use for synthesis front end.
Are there other FOSS synthesis tools for either Verilog or VHDL? What are the limitations?
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