Open Source Synthesis Tools

There's this ASIC design tools suite from Pierre et Marie Curie University in Paris :

Nicolas

Am 02.02.19 um 04:30 schrieb snipped-for-privacy@gmail.com:

I guess the most well-known free simulators are GHDL and Icarus Verilog. Icarus Verilog used to have some synthesis support, but it was dropped. yosys is a well-known current synthesis tool (targeting Xilinx 7-Series and Lattice iCE40 and ASIC). I once used a flow based on Berkely vl2mv, vis, abc, Icarus Verilog to get to a simulated ASIC from Verilog.

I guess there is a lot more out there.

Philipp

W dniu sobota, 2 lutego 2019 04:30:52 UTC+1 u?ytkownik gnuarm.del...@g mail.com napisa?:

L... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any case.

and bit stream generation of the Lattice iCE40 devices, well, some of them anyway. I don't recall what they use for synthesis front end.

e the limitations?

I think that currently the most successful project is Yosys. It supports La ttice and Xilinx 7 series FPGAs.

There's also very nice frontend for Yosys - SymbiYosys, which can be used f or formal verification of RTL code. It supports only Verilog in free versio n, but also VHDL in paid version.

There's also very preliminary VHDL frontend for Yosys based on GHDL:

Adrian