Altera Cyclone replacement

Hi,
We got an old design with an Altera Cyclone FPGA (EP1C12F324).
These are probably obsolete (Can't find any info on them on the Intel
site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV
and Cyclone-V if I understood correctly.
Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of
changes should I expect to code and board? Design includes NIOS.
Or alternatively, are their sources for these old Cyclone chips?
(We actually would need 3 different types :-( )
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Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail) 

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Stef
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Hi Stef,
Try
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there are several distributors that still have some types in stock.
Good luck, Hans
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HT-Lab
Hi,
Are you looking for somebody who can transfer you project from Altera Cyclone to Cyclone V ?
If yes, my email is gorskia @ wp.pl. My small R&D company is looking for new customers.
Best regards
Reply to
Adam Górski
mail)
Wow. The original Cyclone family is really old technology. Do you have th e source for the design and the Nios?
We do a lot of obsolescence respins for customers like this, so yes it is p ossible. Sometimes it requires *some* redesign to target the appropriate p rimitives in the newer families, etc.
I would not recommend targeting the Cyclone IV as that family is pushing 10 years old now. Cyclone V was released 4-5 years ago and Cyclone 10 is the latest in their "low-cost" portfolio. Given the low logic density of the original design, you might consider the MAX10 instead.
Another factor to consider is whether the current design uses the original 16-bit Nios or the 32-bit Nios II. I mention it because a lot of people si mply refer to the Nios II as Nios but when we're talking about porting an o lder design it matters. That may impact how easy it is to port the design.
Reply to
kkoorndyk
Unless device specific features were instantiated, there is little to port. The HDL source should compile without issues. There will be a pinout spe cification file that assigns pin numbers and I/O characteristics which typi cally is device specific. This will need to be redone, but since the packa ge is changing that's not surprising though, is it? Just be sure to keep t he characteristics while changing the pin numbers.
There are often sources for old FPGAs. I am still using a Lattice part tha t was EOL some six years ago.
Rick C.
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gnuarm.deletethisbit
Okay, didn't expect that to be so easy, gues that's one of the reasons I'm not in purchasing. ;-) Turns out at least small quantities are available from Arrow, Avnet, Mouser, etc.
So if we only do one run, this would be sufficient. Thanks.
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Stef
Indeed! Friday I dug up some datasheets from 2007 and found that a bit old already. But Today I found the correct Intel page and it turns out the original Cyclone was launched in 2002! Suddenly remembered I once played with Cyclone a little. Found the old Cyclone II eval kit in a box. :-)
Don't know yet. For now just checking if it's even worth getting it. (always good to have as reference for a new design ofcourse, but for that you do not need a working build environment etc.)
Okay sounds promising. How about board design, package, pinout and supply voltages?
Ah, friday I somehow landed on an Intel page where I only found Cyclone IV and V? Today I found the compte portfolio. ;-)
The largest Cyclone had 20k LEs, the smallest Cyclone 10 already has 85k LEs. MAX 10 ranges from 2k to 50k LEs, so should easely fit.
Don't know yet. Just found the word 'Nios' in the docs we have so far. But thanks for the warning. 16-bit Nios is no longer supported?
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Stef
Okay, not too hard then (probably ;-) ). But if I read correctly, you don't expect pin compatible devices to exist? So board modifications are inevitable.
Yes, found a few already thanks to another reply. But I am a little worried about the future proofness of that approach.
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Stef
Not for now, but who knows. Will be to Cyclone 10 or Max 10 then after recent discoveries. ;-)
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Stef
On 2019-01-28 Stef wrote in comp.arch.fpga:
Oops, smallest Cyclone 10 GX is 85k LEs. But then there is Cyclone 10 LP, which starts at 6k LEs, going up to 120k.
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Stef
-IV
If you are porting to a new family, why limit yourself to Cyclones? If the HDL was written without using specific device features, you can likely por t it as easily to another brand as to a new device. Xilinx and Lattice and even Microsemi make competitive FPGAs. But then I suppose there is a lice nse issue with using NIOS on something other than an Altera part. That's a nother reason why I don't use proprietary code in my designs.
At one time I worked for a company who used a lot of FPGAs. They didn't ha ve brand loyalty. They would use whichever device was best for a given des ign. So their policy was to not use anything specific to a brand... well, for the most part. I recall we got a demonstration one day by my boss who had created a design which needed to be updated. Seems he had included one tiny piece that required hand routing in the chip editor to meet the timin g spec... and had not documented this anywhere!!! So we received a bit of oral tradition. This company makes test equipment that is sold to all the major comms manufacturers. lol!
Given that Altera is now owned by Intel, I would use this opportunity to re place the NIOS processor with something independent of device manufacturer and remove your brand dependency. There are tons of third party processors out there. I can recommend one if you need.
Rick C.
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gnuarm.deletethisbit
On Monday, January 28, 2019 at 6:28:05 AM UTC-5, snipped-for-privacy@gmail.com wr ote:
l
ne-IV
he HDL was written without using specific device features, you can likely p ort it as easily to another brand as to a new device. Xilinx and Lattice a nd even Microsemi make competitive FPGAs. But then I suppose there is a li cense issue with using NIOS on something other than an Altera part. That's another reason why I don't use proprietary code in my designs.
have brand loyalty. They would use whichever device was best for a given d esign. So their policy was to not use anything specific to a brand... well , for the most part. I recall we got a demonstration one day by my boss wh o had created a design which needed to be updated. Seems he had included o ne tiny piece that required hand routing in the chip editor to meet the tim ing spec... and had not documented this anywhere!!! So we received a bit o f oral tradition. This company makes test equipment that is sold to all th e major comms manufacturers. lol!
replace the NIOS processor with something independent of device manufacture r and remove your brand dependency. There are tons of third party processo rs out there. I can recommend one if you need.
This is an excellent point! The company I work for is a design partner for both Brand A/I and Brand X so I'm hesitant speak poorly of either. Howeve r, after the acquisition in 2016, it appears that Intel halted *everything* in the Altera business and they're still catching up with the rebranding o n all of their documentation, website, etc. Their forums are still a real mess, so even searching for solutions is a challenge.
For anyone in the same position as the OP, if the sales volumes and the for ecast are long enough, I'd recommend retargeting another device, preferably Xilinx. If your projected volume is high enough that you aren't going to be able to find drop-in parts on the market, you're going to be looking at a board respin for the new devices (or an interposer, if possible) and some porting effort anyway. You may as well take the opportunity to "future pr oof" the design by migrating to another vendor that isn't likely to get acq uired or axed. Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely over kill for whatever your Nios is doing). Otherwise, the Artix-7 and Spartan- 7 would be good targets if you want to migrate to a Microblaze or some othe r soft core. The Spartan-7 family is essentially the Artix-7 fabric with t he transcievers removed and are offered in 6K to 100K logic cell densities.
Reply to
kkoorndyk
You may as well take the opportunity to "future proof" the design by migrat ing to another vendor that isn't likely to get acquired or axed. Xilinx ha s the single core Zynq-7000 devices if you want to go with a more main-stre am, ARM processor sub-system (although likely overkill for whatever your Ni os is doing). Otherwise, the Artix-7 and Spartan-7 would be good targets i f you want to migrate to a Microblaze or some other soft core. The Spartan -7 family is essentially the Artix-7 fabric with the transcievers removed a nd are offered in 6K to 100K logic cell densities.
I don't think you actually got my point. Moving to a Spartan by using a Mi croBlaze processor isn't "future proofing" anything. It is just shifting f rom one brand to another with the exact same problems.
If you want to future proof a soft CPU design you need to drop any FPGA com pany in-house processor and use an open source processor design. Then you can use any FPGA you wish.
Here is some info on the J1, an open source processor that was used to repl ace a microblaze when it became unequal to the task at hand.
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Rick C.
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gnuarm.deletethisbit
I was under the assumption that porting to Cyclones would be less work than moving to other families/manufacturers. And I think that is still the case if NIOS is part of the existing design.
If it really comes to porting to another architecture, we might even port the whole thing to a microcontroller. As far as we can see now, there was no real need for an FPGA in that design. I/O might be a problem, but that is one of the thing to investigate if it comes to porting.
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Stef
the HDL was written without using specific device features, you can likely port it as easily to another brand as to a new device. Xilinx and Lattice and even Microsemi make competitive FPGAs. But then I suppose there is a license issue with using NIOS on something other than an Altera part. That 's another reason why I don't use proprietary code in my designs.
an
e
Don't suggest to me that an FPGA design should be ported to an MCU. I'm in the other camp that MCU designs can often be effectively ported to FPGAs. I find the issues with sharing a single CPU to perform multiple tasks in r eal time to be much greater than the issues of fitting a design into an FPG A. People cite all sorts of "facts" about using FPGAs that don't seem to a pply in my designs, so I'm not sure what they are doing wrong. I find FPGA s to be easy to design and work with. I also find much fewer problems on t he lab bench and in the field than others do with software based designs.
But certainly the easy route is to continue making the boards with the old parts. Just be careful of your sources and verify each lot of devices you buy before using them in a design. There are a lot of counterfeits these d ays. EOL devices are popular targets.
Rick C.
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gnuarm.deletethisbit
On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, snipped-for-privacy@gmail.com w rote:
ating to another vendor that isn't likely to get acquired or axed. Xilinx has the single core Zynq-7000 devices if you want to go with a more main-st ream, ARM processor sub-system (although likely overkill for whatever your Nios is doing). Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core. The Spart an-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.
MicroBlaze processor isn't "future proofing" anything. It is just shifting from one brand to another with the exact same problems.
ompany in-house processor and use an open source processor design. Then yo u can use any FPGA you wish.
place a microblaze when it became unequal to the task at hand.
No, I got your point perfectly, hence the following part of my recommendati on: "or some other soft core."
If the original Nios was employed, I'm not entirely convinced a soft core i s necessary (yet). How simple is the software running on it? Can it reaso nably be ported to HDL, thus ensuring portability? I tend to lean that way unless the SW was simple due to capability limitations in the earlier tech nologies (e.g., old Cyclone and Nios) and the desire is to add more feature s that are realizable with new generation devices and soft (or hard) core c apabilities.
Reply to
kkoorndyk
grating to another vendor that isn't likely to get acquired or axed. Xilin x has the single core Zynq-7000 devices if you want to go with a more main- stream, ARM processor sub-system (although likely overkill for whatever you r Nios is doing). Otherwise, the Artix-7 and Spartan-7 would be good targe ts if you want to migrate to a Microblaze or some other soft core. The Spa rtan-7 family is essentially the Artix-7 fabric with the transcievers remov ed and are offered in 6K to 100K logic cell densities.
a MicroBlaze processor isn't "future proofing" anything. It is just shifti ng from one brand to another with the exact same problems.
company in-house processor and use an open source processor design. Then you can use any FPGA you wish.
replace a microblaze when it became unequal to the task at hand.
tion: "or some other soft core."
I am making the point that porting from one proprietary processor to anothe r is of limited value. Microblaze is proprietary. I believe there may be some open source versions available, but I expect there are open source ver sions of the NIOS available as well. But perhaps more importantly, they ar e far from optimal. That's why I posted the info on the J1 processor. It was invented to replace a Microblaze that wasn't up to the task.
is necessary (yet). How simple is the software running on it? Can it rea sonably be ported to HDL, thus ensuring portability? I tend to lean that w ay unless the SW was simple due to capability limitations in the earlier te chnologies (e.g., old Cyclone and Nios) and the desire is to add more featu res that are realizable with new generation devices and soft (or hard) core capabilities.
Sometimes soft CPUs are added to reduce the size of logic. Other times the y are added because of the complexity of expression. Regardless of how sim ply we can write HDL, the large part of the engineering world perceives HDL as much more complex than other languages and are not willing to port code to an HDL unless absolutely required. So if the code is currently in C, i t won't get ported to HDL without a compelling reason.
Personally I think Xilinx and Altera are responsible for the present percep tion that FPGAs are difficult to use, expensive, large and power hungry. T hat is largely true if you use their products only. Lattice has been addre ssing a newer market with small, low power, inexpensive devices intended fo r the mobile market. Now if someone would approach the issue of ease of us e by something more than throwing an IDE on top of their command line tools , the FPGA market can explode into territory presently dominated by MCUs.
Does anyone really think toasters can only be controlled by MCUs? We just need a cheap enough FPGA in a suitable package.
Rick C.
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gnuarm.deletethisbit
migrating to another vendor that isn't likely to get acquired or axed. Xil inx has the single core Zynq-7000 devices if you want to go with a more mai n-stream, ARM processor sub-system (although likely overkill for whatever y our Nios is doing). Otherwise, the Artix-7 and Spartan-7 would be good tar gets if you want to migrate to a Microblaze or some other soft core. The S partan-7 family is essentially the Artix-7 fabric with the transcievers rem oved and are offered in 6K to 100K logic cell densities.
g a MicroBlaze processor isn't "future proofing" anything. It is just shif ting from one brand to another with the exact same problems.
GA company in-house processor and use an open source processor design. The n you can use any FPGA you wish.
o replace a microblaze when it became unequal to the task at hand.
dation: "or some other soft core."
her is of limited value. Microblaze is proprietary. I believe there may b e some open source versions available, but I expect there are open source v ersions of the NIOS available as well. But perhaps more importantly, they are far from optimal. That's why I posted the info on the J1 processor. I t was invented to replace a Microblaze that wasn't up to the task.
re is necessary (yet). How simple is the software running on it? Can it r easonably be ported to HDL, thus ensuring portability? I tend to lean that way unless the SW was simple due to capability limitations in the earlier technologies (e.g., old Cyclone and Nios) and the desire is to add more fea tures that are realizable with new generation devices and soft (or hard) co re capabilities.
hey are added because of the complexity of expression. Regardless of how s imply we can write HDL, the large part of the engineering world perceives H DL as much more complex than other languages and are not willing to port co de to an HDL unless absolutely required. So if the code is currently in C, it won't get ported to HDL without a compelling reason.
eption that FPGAs are difficult to use, expensive, large and power hungry. That is largely true if you use their products only. Lattice has been add ressing a newer market with small, low power, inexpensive devices intended for the mobile market. Now if someone would approach the issue of ease of use by something more than throwing an IDE on top of their command line too ls, the FPGA market can explode into territory presently dominated by MCUs.
t need a cheap enough FPGA in a suitable package.
]>Microblaze is proprietary. I believe there may be some open source versi ons available, but I expect there are open source versions of the NIOS avai lable as well.
Microblaze clones: aeMB, an-noc-mpsoc, mblite, mb-lite-plus, myblaze, openf ire_core, openfire2, secretblaze
No NIOS clones that I know of
]>But perhaps more importantly, they are far from optimal. Ugh, they have some of the best figure-of-merit numbers available. (Instructions per second per LUT) And are available in many configuration options.
There are a large variety of RISC-V cores available some of which have low LUT counts.
Jim Brakefield
Reply to
jim.brakefield
On Wednesday, January 30, 2019 at 7:42:54 PM UTC-5, snipped-for-privacy@ieee.org wro te:
y migrating to another vendor that isn't likely to get acquired or axed. X ilinx has the single core Zynq-7000 devices if you want to go with a more m ain-stream, ARM processor sub-system (although likely overkill for whatever your Nios is doing). Otherwise, the Artix-7 and Spartan-7 would be good t argets if you want to migrate to a Microblaze or some other soft core. The Spartan-7 family is essentially the Artix-7 fabric with the transcievers r emoved and are offered in 6K to 100K logic cell densities.
ing a MicroBlaze processor isn't "future proofing" anything. It is just sh ifting from one brand to another with the exact same problems.
FPGA company in-house processor and use an open source processor design. T hen you can use any FPGA you wish.
to replace a microblaze when it became unequal to the task at hand.
endation: "or some other soft core."
other is of limited value. Microblaze is proprietary. I believe there may be some open source versions available, but I expect there are open source versions of the NIOS available as well. But perhaps more importantly, the y are far from optimal. That's why I posted the info on the J1 processor. It was invented to replace a Microblaze that wasn't up to the task.
core is necessary (yet). How simple is the software running on it? Can it reasonably be ported to HDL, thus ensuring portability? I tend to lean th at way unless the SW was simple due to capability limitations in the earlie r technologies (e.g., old Cyclone and Nios) and the desire is to add more f eatures that are realizable with new generation devices and soft (or hard) core capabilities.
they are added because of the complexity of expression. Regardless of how simply we can write HDL, the large part of the engineering world perceives HDL as much more complex than other languages and are not willing to port code to an HDL unless absolutely required. So if the code is currently in C, it won't get ported to HDL without a compelling reason.
rception that FPGAs are difficult to use, expensive, large and power hungry . That is largely true if you use their products only. Lattice has been a ddressing a newer market with small, low power, inexpensive devices intende d for the mobile market. Now if someone would approach the issue of ease o f use by something more than throwing an IDE on top of their command line t ools, the FPGA market can explode into territory presently dominated by MCU s.
ust need a cheap enough FPGA in a suitable package.
sions available, but I expect there are open source versions of the NIOS av ailable as well.
nfire_core, openfire2, secretblaze
w LUT counts.
Not sure what figures you are talking about. Has anyone compiled a compari son?
Rick C.
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gnuarm.deletethisbit
rote:
:
by migrating to another vendor that isn't likely to get acquired or axed. Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely overkill for whatev er your Nios is doing). Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core. T he Spartan-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.
using a MicroBlaze processor isn't "future proofing" anything. It is just shifting from one brand to another with the exact same problems.
y FPGA company in-house processor and use an open source processor design. Then you can use any FPGA you wish.
ed to replace a microblaze when it became unequal to the task at hand.
mmendation: "or some other soft core."
another is of limited value. Microblaze is proprietary. I believe there m ay be some open source versions available, but I expect there are open sour ce versions of the NIOS available as well. But perhaps more importantly, t hey are far from optimal. That's why I posted the info on the J1 processor . It was invented to replace a Microblaze that wasn't up to the task.
t core is necessary (yet). How simple is the software running on it? Can it reasonably be ported to HDL, thus ensuring portability? I tend to lean that way unless the SW was simple due to capability limitations in the earl ier technologies (e.g., old Cyclone and Nios) and the desire is to add more features that are realizable with new generation devices and soft (or hard ) core capabilities.
es they are added because of the complexity of expression. Regardless of h ow simply we can write HDL, the large part of the engineering world perceiv es HDL as much more complex than other languages and are not willing to por t code to an HDL unless absolutely required. So if the code is currently i n C, it won't get ported to HDL without a compelling reason.
perception that FPGAs are difficult to use, expensive, large and power hung ry. That is largely true if you use their products only. Lattice has been addressing a newer market with small, low power, inexpensive devices inten ded for the mobile market. Now if someone would approach the issue of ease of use by something more than throwing an IDE on top of their command line tools, the FPGA market can explode into territory presently dominated by M CUs.
just need a cheap enough FPGA in a suitable package.
ersions available, but I expect there are open source versions of the NIOS available as well.
penfire_core, openfire2, secretblaze
low LUT counts.
rison?
Altera/Intel: "Nios II Performance Benchmarks Xilinx: appendix of MicroBlaze Processor Reference Guide
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jim.brakefield

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