I have successfully compiled some ISE's (version 6.x and 7.x) with aldecs tools (riviera), and made a Makefile (see below) for this, hope it helps. Haven't tried later versions yet. (I'm running this in a cygwin/XP environment.)
I think there are aldec specifics around using/finding the "smartmodels" you need for simulating PPCs, MGTs etc. using swift libraries, but i'm on thin ice here.
So far my experience with riviera is good, slower (than the M* simulator) in the elaboration, but atleast as fast during simulation.
Regards /Pontus
# # Makefile to compile xilinx libs for the riviera simulator # # Existing libraries: # unisim simulation models of unisim components # simprim simulation models of post PAR components with vital timing # xilinxcorelib simulation models of coregen components (needs unisim)
# First we need to create the library file, then compile the source into # that library. # I don't create an aldec "global" library, since the version of xilinx # should be set by my specific design, not the simulator.
# Before running this makefile you must setup paths to the the tool(s). # First check some environment variables. ifeq ($(XILINX),) $(error XILINX environment variable not set) endif
# -93 : vhdl language revision # -o : automatic file ordering VCOM_OPTS := -93 -o
.PHONY : all all : unisim xilinxcorelib simprim
################################################################ # unisim ################################################################ .PHONY : unisim unisim : unisim_vlib.log unisim_vcom.log
unisim_vlib.log : vlib unisim | tee $@
unisim_files := ${XILINX}/vhdl/src/unisims/*.vhd unisim_vcom.log : vcom ${VCOM_OPTS} -work unisim ${unisim_files} | tee $@
################################################################ #simprim ################################################################ .PHONY : simprim simprim : simprim_vlib.log simprim_vcom.log
simprim_vlib.log : vlib simprim | tee $@
# dont use any of the _mti files simprim_files := $(filter-out %_mti.vhd,$(wildcard ${XILINX}/vhdl/src/ simprims/*.vhd)) simprim_vcom.log : vcom ${VCOM_OPTS} -work simprim ${simprim_files} | tee $@
################################################################ # xilinxcorelib (needs unisim to be compiled first) ################################################################ .PHONY : xilinxcorelib xilinxcorelib : unisim xilinxcorelib_vlib.log xilinxcorelib_vcom.log
xilinxcorelib_vlib.log : vlib xilinxcorelib | tee $@
# Remember this_pwd so to avoid specifying source paths for vcom. this_pwd := $(shell cygpath -m `pwd`) # -s tells vcom to use the library.cfg in this folder # -d tells vcom to use this folder for tmp files # vhdl_analyze_order is a xilinx file listing all coregen files, # and their proper analysis order. xilinxcorelib_vcom.log : cd ${XILINX}/vhdl/src/XilinxCoreLib/; \ vcom ${VCOM_OPTS} -work xilinxcorelib \ -s $(this_pwd) \ -d $(this_pwd) \ -f vhdl_analyze_order | tee $(this_pwd)/$@; \
################################################################ # clean ################################################################ # Aldec leaves a number of different files behind if compile is interupted... .PHONY : clean clean : rm -f library.cfg *.dag *.tmp *.epr *.bin *.log *.opr *.top rm -rf unisim simprim xilinxcorelib
.PHONY : check check : unisim_vlib.log unisim_vcom.log simprim_vlib.log simprim_vcom.log xilinxcorelib_vlib.log xilinxcorelib_vcom.log cat $^ | grep -i err
# last line