Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support

I've noticed Modelsim directly compiles the vendor's simulation-libraries from the HDL-source (either VHDL or Verilog.) I simply run the library-generator applet that comes with ISE/EDK.

But Aldec seems to distribute the same vendor library-update in the form of a download, up to a month later.

Could an Aldec user explain why this is the case? Can the Aldec simulator compile the libraries directly? Or are there incompatibilities if you try to do this yourself (and hence, the Aldec official library-update.)

I really wanted to mention Aldec as an alternative to Modelsim/PE, but before I do that, I'd like to get this cleared up.

Reply to
kookoo4systemverilog
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Those libraries are available anytime on the device vendor sites. The device *vendors* A and X provide this "service" for their own devices with their oem modelsim tools, perhaps in hope that I chose their non-portable netlists over their synthesis tools.

  1. Aldec is not an oem for the major brands, however...
  2. Compiling a library is not a big deal and ...
  3. If I am using synthesis, I don't need any libraries for simulation. Use the source Luke.

-- Mike Treseler

Reply to
Mike Treseler

Ok, so there are no issues with the user re-compiling the Verilog/VHDL simprim, unisims, xilinxcorelib, from source? That's what I wanted to hear. I was worried that the vendor's libs used weird (non-standard) Verilog modeling, and that it might not work 'out of the box' with non-Modelsim simulators.

(My coworker told me this was a BIG problem with the whole Verilog scene in general, back when the original Verilog-XL was king.)

?!? If your synthesizeable-RTL only uses generic statements (i.e. infered FPGA-structures) , and not hand-instantiations, I can understand. But what about when you instantiate specific I/O-cells, or a DCM? Don't those have to come from the library?

And let's not forget Xilinx's Smartmodels for the TEMAC, Microblaze, among other IP. (I hope the Smartmodel 10.1i installer has finally gotten around to supporting Windows/Vista.)

Reply to
TSIuser

I have heard nothing but good reports about Aldec.

That's my style.

Only if I need PLL or DCM over a generic phase accumulator and then only if I choose to use the vendor model.

See page 8 of

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"FPGA SmartModel Obsolescence Notes Effective December 1st 2003, the Synopsys FPGA SmartModel simulation models that are offered as part of the DesignWare Library will be obsolete. This section documents the transition and technical support plans."

-- Mike Treseler

Reply to
Mike Treseler

I have successfully compiled some ISE's (version 6.x and 7.x) with aldecs tools (riviera), and made a Makefile (see below) for this, hope it helps. Haven't tried later versions yet. (I'm running this in a cygwin/XP environment.)

I think there are aldec specifics around using/finding the "smartmodels" you need for simulating PPCs, MGTs etc. using swift libraries, but i'm on thin ice here.

So far my experience with riviera is good, slower (than the M* simulator) in the elaboration, but atleast as fast during simulation.

Regards /Pontus

# # Makefile to compile xilinx libs for the riviera simulator # # Existing libraries: # unisim simulation models of unisim components # simprim simulation models of post PAR components with vital timing # xilinxcorelib simulation models of coregen components (needs unisim)

# First we need to create the library file, then compile the source into # that library. # I don't create an aldec "global" library, since the version of xilinx # should be set by my specific design, not the simulator.

# Before running this makefile you must setup paths to the the tool(s). # First check some environment variables. ifeq ($(XILINX),) $(error XILINX environment variable not set) endif

# -93 : vhdl language revision # -o : automatic file ordering VCOM_OPTS := -93 -o

.PHONY : all all : unisim xilinxcorelib simprim

################################################################ # unisim ################################################################ .PHONY : unisim unisim : unisim_vlib.log unisim_vcom.log

unisim_vlib.log : vlib unisim | tee $@

unisim_files := ${XILINX}/vhdl/src/unisims/*.vhd unisim_vcom.log : vcom ${VCOM_OPTS} -work unisim ${unisim_files} | tee $@

################################################################ #simprim ################################################################ .PHONY : simprim simprim : simprim_vlib.log simprim_vcom.log

simprim_vlib.log : vlib simprim | tee $@

# dont use any of the _mti files simprim_files := $(filter-out %_mti.vhd,$(wildcard ${XILINX}/vhdl/src/ simprims/*.vhd)) simprim_vcom.log : vcom ${VCOM_OPTS} -work simprim ${simprim_files} | tee $@

################################################################ # xilinxcorelib (needs unisim to be compiled first) ################################################################ .PHONY : xilinxcorelib xilinxcorelib : unisim xilinxcorelib_vlib.log xilinxcorelib_vcom.log

xilinxcorelib_vlib.log : vlib xilinxcorelib | tee $@

# Remember this_pwd so to avoid specifying source paths for vcom. this_pwd := $(shell cygpath -m `pwd`) # -s tells vcom to use the library.cfg in this folder # -d tells vcom to use this folder for tmp files # vhdl_analyze_order is a xilinx file listing all coregen files, # and their proper analysis order. xilinxcorelib_vcom.log : cd ${XILINX}/vhdl/src/XilinxCoreLib/; \ vcom ${VCOM_OPTS} -work xilinxcorelib \ -s $(this_pwd) \ -d $(this_pwd) \ -f vhdl_analyze_order | tee $(this_pwd)/$@; \

################################################################ # clean ################################################################ # Aldec leaves a number of different files behind if compile is interupted... .PHONY : clean clean : rm -f library.cfg *.dag *.tmp *.epr *.bin *.log *.opr *.top rm -rf unisim simprim xilinxcorelib

.PHONY : check check : unisim_vlib.log unisim_vcom.log simprim_vlib.log simprim_vcom.log xilinxcorelib_vlib.log xilinxcorelib_vcom.log cat $^ | grep -i err

# last line

Reply to
pontus.stenstrom

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