I am having difficulties in trying to deskew the Clock on a synchronous local bus interface between a Virtex4 FPGA and a PowerPC chip.
The instantiation port map of a DCM to provide 0 phase-shift between the external LCLK_IN and the internal CLK is shown below.
--------------------- port map ( CLK0 => CLK, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => open, -- DCM LOCK status output CLKFB => CLK, -- DCM clock feedback CLKIN => LCLK_IN, -- Clock input (from IBUFG, BUFG or DCM) RST => RESET -- DCM asynchronous reset input );
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The timing constraint is shown below; I believe that the OFFSET constraints should be effective since the phase-shift, 0 in this case, due to the DCM on LCLK_IN, is accounted for by the PAR tool.
--------------------- NET "LCLK_IN" TNM_NET = LCLK_IN; TIMESPEC TS_LCLK_IN = PERIOD "LCLK_IN" 10 ns HIGH 50%; OFFSET = IN 8 ns BEFORE "LCLK_IN"; OFFSET = OUT 7 ns AFTER "LCLK_IN";
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A portion of the timing report (.twr) is shown below: Note the Clock Path Delay of 4.979ns which the DCM usage has failed to eliminate in this attempt. I was expecting that the delay would be 0ns or very close to 0ns.
--------------------- Slack: -5.472ns (requirement - (clock arrival + clock path
- data path + uncertainty)) Source: READY_CARRIER (FF) Destination: LAD (PAD) Source Clock: CLK rising at 0.000ns Requirement: 7.000ns Data Path Delay: 7.313ns (Levels of Logic = 3) Clock Path Delay: 4.979ns (Levels of Logic = 3) Clock Uncertainty: 0.180ns : : Maximum Clock Path: LCLK_IN to READY_CARRIER Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- D14.I Tiopi 0.963 LCLK_IN LCLK_IN LCLK_IN_IBUFG DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.260 LCLK_IN_IBUFG DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -2.213 DCM_BASE_inst DCM_BASE_inst BUFGCTRL_X0Y23.I0 net (fanout=3) 1.504 CLK1 BUFGCTRL_X0Y23.O Tbgcko_O 0.900 CLK_BUFG CLK_BUFG SLICE_X52Y103.CLK net (fanout=123) 2.565 CLK -------------------------------------------------
--------------------------- Total 4.979ns (-0.350ns logic,
5.329ns route)---------------------
Can anyone shed light on this problem?
Bill Ngo