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Hi,

Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx).

The bad news(?): I will still participate here on c.a.f. and my Xilinx blog (is that of any use to anyone?) and I am still willing to find the answers to those questions that seem not to have any answers in our documentation, or on our website.

The good news(?): I no longer manage the FPGA Lab (silicon verification and characterization planning, testing, and coordination). That has been re-organized, and its role expanded (which is all goodness).

The best news(?): I am part of Xilinx Labs (the research side of Xilinx), where I get to do lots of useful and practical stuff, as well as try to peer into the future.

I wish to thank those that emailed me personally and expressed any concerns for me: I have fairly diverse and useful talents, so finding a place where I fit in in the new organization was never a concern.

I regret that there were those that did not fit in to the new structure, and as I have said before, I wish them the best, and I would recommend them highly to anyone.

Austin

Reply to
austin
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Uh oh, so much for having accurate timing files for Virtex-6 :-)

I don't understand the reorganization either, other than in cynical excuse for an executive bonus terms. XLNX stock price was a little low at the beginning of this year, but not terribly low. It came back without this action. The price has pretty much tracked ALTR so you can't say that X was doing anything terribly wrong.

On the other hand, FPGA stock prices have been flat since the 2000 boom- I don't see how a re-organization is going to change this. Maybe if Xilinx entered a new market...

--
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Reply to
Joseph H Allen

Joseph,

I do understand the reorganization.

And, it was not to increase executive bonuses.

It was to better serve our customers.

Time will only tell, but I think that it is a very good thing.

Rather re-org while on top to get even better, than to re-org (down-size) because there is no money.

This was not a re-org to down-size. 7% hardly matters in terms of the costs. But putting 93% in the right positions to get things done right, is critical to future success.

And the executives have the same "pay for performance" that everyone else faces: they need to show tangible progress and meet their goals, or else their jobs are likely to "go-away."

Austin

Reply to
austin

Glad you are happy with the results of the re-org! Best wishes for the future in your new position.

I tend to use Xilinx products in some really unusual ways, almost never as straightforward digital "blocks". In one case, due to the number of I/Os required, I have a Spartan XCS20 used as a motherboard slot manager, where it controls passing tokens across vacant card slots and reading out the population status of those slots. Except when reading out the status info, it is totally combinatorial.

Another project some years ago was using a bunch of 95xxx series chips largely as flip-flops. We had a multi-channel delay device using the AD9501 programmable delay chip, but we wanted it to work like a one-shot, not a delay. So, I needed a LOT of FFs on each board. I looked at other vendor's products, and everybody had their FFs set up to use global clocks, ONLY, no way to individually clock them. Xilinx, however, always has a switch to allow the logic fabric to provide clocks to the FFs.

I hope Xilinx will continue to provide these special "hooks" that allow us to do really oddball applications with their FPGAs and CPLDs.

Jon

Reply to
Jon Elson

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