Hi,
There are three sources for plb master interface.
1) plb_master_single.vhd and plb_master_burst.vhd use a combined read- write controller for the qualifier signals.
2) plb_master.vhd has a split bus architecture that give separate read and write qualifier signals.
-I want to use the split bus architecture but the EDK plbv46 IPIF generator generates interfaces that have the combined read write controller. What procedure should I follow in 'Create/Import Peripheral' to generate IPIF that uses split bus architecture.
-Also, can I instantiate plb_master directly into IPIF instead of plb_master_burst? So I can use the separate read and write qualifiers.
Thanks and Regards,
Tejaswy Hari