Field-Programmable Gate Arrays

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Trouble programming V4FX40

A working board has been respun to use a FX40 in place of a FX20. For some reason I can't program FPGA on the new board...
22 comments posted 18yrs
posted by mbmsv
22 comments posted 18yrs posted by mbmsv

Altera Quartus Web Edition 8.0 available

I've just had an email from Altera about the availability of Quartus Web Edition 8.0. I'm in the process of downloading...
6 comments posted 18yrs
posted by leon355
6 comments posted 18yrs posted by leon355

Cheating the FPGA clock speed

Hey all -- So I've got a design, the very vaguest outlines of which are beginning to gel. But one of the things that's...
9 comments posted 18yrs
posted by rgaddi
9 comments posted 18yrs posted by rgaddi

Whitepapers are taking over the lost TechXclusives

Thanks for the whitepaper, Peter! WP335 - Creative Uses of Block RAM http://www.xilinx.com/support/documentation/white_...
4 comments posted 18yrs
posted by newsgroup
4 comments posted 18yrs posted by newsgroup

Strange Virtex-4FX 8b10b encoding behaviour

Hi, im an sending with an Virtex4-FX 8b10b encoded data at 1.25Gbps. It is working fine in simulation, but the implemen...
0 comments posted 18yrs
posted by ksulimma
0 comments posted 18yrs posted by ksulimma

bape ked robot red monkey adidas jacket

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0 comments posted 18yrs
posted by shoeshiveb
0 comments posted 18yrs posted by shoeshiveb

Error while compiling uClinux image for Microblaze

Hi, I was trying to compile uClinux image for microblaze. For doing so I followed the step by step process given in htt...
0 comments posted 18yrs
posted by mehrotrasaransh
0 comments posted 18yrs posted by mehrotrasaransh

FSM running with unstable clock

Hi, I have described a state machine running with an external pixel clock. As I could see on the oscilloscope the ScanD...
4 comments posted 18yrs
posted by ALuPin
4 comments posted 18yrs posted by ALuPin

fpga reprogrammable?

hi.... how many times cain i download .bit files onto an fpga? i use virtex2pro.... thanks vikram
8 comments posted 18yrs
posted by vikram788
8 comments posted 18yrs posted by vikram788

aurora channel initialization fails

hi, I am trying to run the aurora example given by xilinx on fpga board which have xc2vp50 I am using refclock which is...
0 comments posted 18yrs
posted by ajith.thamara
0 comments posted 18yrs posted by ajith.thamara

how to track down an optimised away signal

Using verilog and ISE 10.1. I add a reg to modify the design's behaviour. It works and it works correctly. The change i...
7 comments posted 18yrs
posted by andy
7 comments posted 18yrs posted by andy

readmem[b|h]

"readmemh" or "readmemb" in Verilog for initializing memories should only work in simulations and not for ASICs, but I'...
2 comments posted 18yrs
posted by camwwang
2 comments posted 18yrs posted by camwwang