Hello,
I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that has a 50 pin IO bank. When I load up a design, and route signals to different parts of this IO region, some of the signals are weakly coupled together. In specific, although they are not the same signal, they only have 50 ohms of resistance between them and are coupling somehow. How do I fix this?