Hello,
I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that has a 50 pin IO bank. When I load up a design, and route signals to different parts of this IO region, some of the signals are weakly coupled together. In specific, although they are not the same signal, they only have 50 ohms of resistance between them and are coupling somehow. How do I fix this?
Is this an output affecting another output, or affecting an input? How strong is the effect (what is the voltage ratio between the driving signal and the affected signal)? Have you observed the common Vcco and common ground. Are there decoupling problems? How did you measure the 50 Ohms? Lots of questions... Peter Alfke, Xilinx Applications
I would not call 50 Ohms is 'weakly coupled'. That is of the order of a termination resistance, so check there are none on the PCB, and none enabled inside the FPGA. If you remove power, does it still measure 50 ohms.
-jg
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