Processor Debug interface

Hi all, I wanted to know about the different debug interfaces used(or standards present like JTAG etc...) in a wireless SOC having a RISC processor. ARM uses some thing called trace debugging, I didn't get the concept clearly. Can anyone enlighten me on the same. I know about JTAG. Thanks, Vittal

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vits ha escrito:

I once did something that could be called "trace debugging". Basically I created a lot of debug signals in the design. Those were connected to a debug module. In this module, I selected a subset of them (the others were automatically removed by the toolchain). The module contained a FIFO memory wide enough to hold N samples of the subset. It also looked for a trigger. When triggered, it started to sample the signals into the FIFO. Depending on the configuration it either sampled on every clock, or when any of the sampled signals changed.

Once the FIFO was full, I could read it from its other side. I made a little software to format it into something readable.

With this little helper I found various bugs that seemed to only appear under very rare and difficult-to-simulate conditions.

Maybe the ARM thing is something similar.


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