VHDL code for RCOM message

Oh my.

I'm not sure how to find the end of packet, but once I figured that out, I would shift a packet in and verify the parity to start with.

Hope you work it out. Until then, I'll be on airbus ;)

-- Mike Treseler

I wonder how fast it needs to be for a spoiler. Do you really use a FPGA for controlling the spoiler or is it just in the test equipment? FPGAs are very complex, synthesizer software and hardware. It is easy to write VHDL programs, which e.g. enter illegal statemachine states, if input signals are not aligned to clock. Unless you write big and time consuming testcases, maybe you won't detect such bugs.

I would use a microcontroller for both, then it is only some lines of C code (or maybe SparkADA, which is better for mathematical proving programs for critical systems).

If this is not a student project then I would suggest you look into assertions (used with a formal tool and not a simulator). This is the only way to test something exhaustively. PSL/SVA are not complicated languages but I would still recommend going onto a course even if it is only 1 day.

In the meantime I will join Mike on Airbus :-)

Hans