XST not inferring distributed RAM

Apr 16, 2006 2 Replies
J

All-



I cannot seem to coax XST to infer a distributed RAM -- I believe it should find a simple, single-port, asynchronous read instance, but I continue to get the dreaded rejection notice "N flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices..."



I have included a simplified version of my code below.



Is the word "assign" necessary for output? I would think not since the output is still continuous / combinatorial.



If anyone has suggestions for key syntax that I'm missing...


-Jeff



reg [1:0] index; reg [3:0] mem [3:0]; /* declare RAM to hold series of 4-pin IO array values */ integer i, j;



always @(posedge clk) begin /* store mem values */



if (reset) index = 0; else index = index + 1;



for (i=0; i


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J

Jeff, I'm not a Verilog guy, but my first suggestion is that your index order is reversed. With a memory array, the index nearest the identifier is the address, while the outer index addresses the bits of the vectors in the array. You may also be able to simplify things by skipping the bit iterations altogether and writing something like:

always @(posedge clk) begin /* store mem values */ if (reset) index = 0; else index = index + 1; mem[index]

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J

John-

I had wanted to store the IO values "vertically", each column representing a bit-cell, because the IO pins carry multiple parallel bitstreams... but based on your advice I stored them horizontally and re-arranged other code to match. And that did work -- although I ended up with several distributed RAMs inferred, because read accesses occur in various ways.

But it does save one heck of a lot of flip-flops and at least I've a grip now on how XST wants to deal with distributed RAM... thanks John.

-Jeff

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