How to generate a signal on Xilinx Spartan II


I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope to hear some noise. My VHDL code, tested on PeakVHDL simulator does generate the waveform and is pasted at the far bottom. The problem is that the code does not compile on Xilinx because "WAIT for 2.5 ns" is not supported on Xilinx Spartan II for a process. What would be the simplest way out to generate 400 approx Hz on a Xilinx 200MHz device? I have used

200MHz/(2 to the power of 19) = 382 Hz approx. (Use MSB of 19 bits of STD_LOGIC_VECTOR)

Another thing which has confused me is: If I wish to write an entity(below) for Spartan II, does the programmer worry about generating the signal for "clk" input? Or simply connect it to the correct pin of FPGA and I should get the signal of 200MHz?

ENTITY some_entity IS PORT (clk : IN BIT); END some_entity;

For my code tested on PeakVHDL, I have generated the 200MHz signal using a test bed(music_tester) and then modified it to 400Hz.

I apologise if the question is basic.

Thanks in advance

ENTITY music_tester IS PORT (clk : OUT STD_LOGIC; freq : IN STD_LOGIC); END music_tester;

ARCHITECTURE behavioral OF music_tester IS BEGIN process BEGIN clk

Reply to
Rakesh Sharma
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The "WAIT..." statement is not synthesisable. You simply need a counter (ripple counter will do) to divide the clock down to 400 Hz or so. Write the VHDL for a toggle flip-flop and string lots of them together - not very elegant but it should work.


Reply to
Leon Heller


I'm not sure I understand the question but :

The CLK input MUST be provided by external means like a Crystal Oscillator and must be directed to an appropriate pin on the FPGA.

Then you must use constrainsts so that your VHDL nets that should be connected to the outside are locked onto the right pads of the FPGA (depends on your board design).


Reply to
Sylvain Munaut

I know XST will infer a counter from

reg [31:0] ctr always @(posedge clk) begin reg = reg + 1 end

Far easier than stringing flops to get a binary countdown.

Nicholas C. Weaver.  to reply email to "nweaver" at the domain
Reply to
Nicholas Weaver

The best solution is to use a phase accumulator (aka Direct Digital Synthesis). All that is is a fancy name for an accumulator that adds a fixed increment value to itself on every clock cycle. The MSB of the accumulator is the clock output, and the output frequency is related to the master clock frequency by:

fo = fc*n/(2^k)

where: fo = output frquency fc = master clock frequency n = increment value (integer) k = number of bits in accumulator.

For example, you have a 200 MHz master clock, and you need the output to be 400 Hz. Lets say we use an 32 bit accumulator, so n = 400/200M * (2^32) = 8589.9, which rounded is 8590. Plugging that back in, you have an output frequency of 400.003 Hz. The number of bits in the accumulator sets the resolution of the frequency setting you can have. The output will have a maximum jitter of +/- 1/2 clock period of the master clock.

The circuit is just an accumulator that always adds the constant n to itself. This works by taking advantage modulo arithmetic. Basically , you keep accumulating the fractional part and throwing away the integer part of the accumulated sum. Each time the sum crosses over to the next integer, the integer part is dropped.

Rakesh Sharma wrote:




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Reply to
Ray Andraka

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