Hello,
in my design I'm using an Array "temp" and want it to by inferred as BlockRAM. But the xst (9.1) only implements it on distibuted RAM:
INFO:Xst:2664 - HDL ADVISOR - Unit : The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently u nsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
----------------------------------------------------------------------- | ram_type | Distributed | |
----------------------------------------------------------------------- | Port A | | aspect ratio | 22-word x 32-bit | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to internal node | | | doA | connected to internal node | |
----------------------------------------------------------------------- | Port B | | aspect ratio | 22-word x 32-bit | | | addrB | connected to signal | | | doB | connected to internal node | |
-----------------------------------------------------------------------
I've looked through my design, but I can't find any asynchronous read? Can anybody please take a look at this?
architecture behav of lsp_to_lpc is type STATE_TYPE is (WAITING, PART1, PART1_2, PART2, PART3, PART3_1, PART3_2, PART3_3, PART3_4, PART4, PART5, PART6, PART7, PART7_1, WRITE_OUT); signal STATE : STATE_TYPE; type memory_20B is array (0 to 9) of signed (15 downto 0); signal lpc : memory_20B; type memory_17_5B is array (0 to 9) of signed (13 downto 0); signal lsp : memory_17_5B; signal lsp_idx, lsp_idx2, lpc_idx : integer range 0 to 9; type memory_88B is array (0 to 21) of signed (31 downto 0); signal temp : memory_88B; signal temp_idx1, temp_idx2 : integer range 0 to 21; signal xout1, xout2, xin1, xin2 : signed (31 downto 0); signal i : integer range 0 to 20; signal j : integer range 0 to 11; signal started : std_logic; signal tmp_a, tmp_b : signed (31 downto 0); begin main : process (CLOCK, RESET) variable temp_a, temp_b : signed (31 downto 0); begin if (RESET = '1') then STATE