XST cant compile with blaxkboxes.

MyProj\xst\work\vlg## latency?

I found that, if I perform re-synthesis after deleted some modules from my source codes, the MyProj\xst\work\vlg## doesn't reflect this change. As a result, at re-synthesis, even if I have a question mark on some modules, meaning the module source files are absent, the XST is still able to synthesize the design, does it mean it searches the MyProj\xst\work\vlg## to look for the missing modules?

Hope somebody can explain this mystery...

Best Regards, Kelvin

Kelvin,

Based off of your description it sounds like compiled modules are remaining in the work directory after you remove the modules. This should not be normal XST behavior.

As for the black box problem, whenever you instantiate a black box in Verilog you have to have a "module declaration." This is required so that the synthesis tool will know which ports are input/output/inout ports. A module declaration is an empty module that contains only the port listing and port declarations:

module top (a,b,c); input a,b; output c;

black_box u1 (.a(in1), .b(in2), .c(out1));

endmodule

module black_box (in1,in2,out1); input in1,in2; output out1;

endmodule

Steve

Kelv> MyProj\xst\work\vlg## latency?