Xilinx ISE ignores Max Fanout

I had been working with Xilinx ISE 12.4 for a while trying to improve the performance of a SPARC based processor.

Till now, I was always and stopping at the "Synthesize - XST" step. I found that going into the "Process Properties" -> "Xilinx Specific Options" for the synthesis process and reducing Max Fanout from 500, down to between

40-16 got me timing closure with not too much additional area. Which is nice.

Now, I need to generate a bitfile and therefore need a proper Xilinx license. Unfortunately, I have access only to a license for ISE 11 (from my university).

So, I installed 11.1, set the max fanout the same way as earlier, and re ran XST. I now find that this max fanout is ignored (lots of FFs with fanouts > 100 and correspondingly large delays) and this causes timing requirements to not be met.

I googled around, and found a couple of suggestions:

  1. Switch off "Resource Sharing" under "HDL Options"
  2. Switch off "Equivalent Register Removal" under "Xilinx Specific Options"

  1. Make sure "Register Duplication" is on (which it always was)

At least #2 seemed to make sense because I felt that equivalent register removal conflicts with the goal of max fanout. So I did all this.

=> Still, max fanout seems to be ignored.

I have also looked at the Xilinx Constraints Guide and it does not clearly tell when global max fanout is ignored. In fact it goes into detail explaining an example where a module specific max fanout (defined in the xcf file) is ignored, but it says nothing about global max fanout. It does say that really low values are not always followed. But a fanout of 100 where the max defined as 16 seems a bit too much.

So why does this happen? There is no difference between the sources I used for 12.4 and am now using for 11.1.

More importantly, how can I fix this?

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