I've been comparing the tools recently:
Altera: the built in synthesis tool is quite good, almost on par with Synplicity (xst is nowhere near as good). This makes Altera's tools a much better value. Also, the time to get going with SOCP is less than with Xilinx EDK. SOCP is more integrated with Quartus-II.
On the other hand, Altera does not have fpga_editor: the low level chip editing tool. It has a tool (chip editor), but you can not modify the routing with it. Instead to make a change you have to basically rerun the place and route. Of course if you are substantially changing your design with fpga_editor, you have other problems... Keep in mind that you can make macros with fixed routing by hand with fpga_editor (useful for delay lines).
If you like scripting and hate GUIs, you will not like Altera. Sure, you can start with the GUI and then generate a script to recompile everything, but you can't start a new design with all scripts. For example, to use chip features (like PLL) you run a wizard to generate or modify "megafunction" macros which you then instantiate in your HDL design files. Also you need the GUI to enter timing and placement constraints (theoretically you could do it with text, but there's no documentation). For complex functions, the wizard is probably better, but scripting people will still not like it.
Also, it's all one monolithic tool: the different functions are not really exposed and the database is very closed. You do not get to see the output from one function and the input to another, or where one ends and another begins. Instead there is an integrated database which each tool accesses. This makes a 'makefile' somewhat meaningless.
Xilinx is definitely much better for scripting: each tool in the flow documents its input files, output files and command line options. I run each tool in a separate directory so that I can clearly see what each one does.
You can do an entire design with just a text editor. For simple chip features you can usually get by looking at the black box definition in the Synplicity "virtex2.v" file (or whichever).
You really need to get Synplify. Unfortunately the EDK does not work well with a Synplicity flow. (IMHO, Xilinx should just buy Synplify). An example of the scripting nature of the Xilinx tools is this: for Altera SOCP, the merge of your program's .elf file with the bitstream happens magically (it's buried in the tools, it works, so don't worry about it).
With Xilinx, it doesn't work right away (because Synplicity and EDK and ProjNav are not integrated), but by the time you get it working you understand how ngdbuild takes a .bmm file as input, and bitgen creates a new .bmm file on output and you are ready to make a script, understand the .bmm file syntax and are thinking about how to load other non-program data into block RAMs, now that you understand how it works.
On the other hand, Xilinx's GUI is not as clear as Altera's and there is definitely a big learning curve to master the tools.
Anyway to summarize: Altera is more like Borland-C and Xilinx is more like Microsoft C (if you were a C programmer in 1989 you would understand :-).