Xilinx V4 not registering T at OLOGIC

Synthesis works from port to port. Maybe mem_t affects no top output port.

-- Mike Treseler

Seems like they are there. I can see them in the editor. They route through several hierarchies to a series of these:

iobuf00 : IOBUF port map ( O => O( 0), IO => IO( 0), I => I( 0), T => T( 0) );

which are there but the OLOGIC is showing a latched O and a thru T.

Brad

Brad Smallridge schrieb:

see below XLXI_7

maps into T flop of ologic 100% antti

XLXI_6 : OFDT_MXILINX_t4 port map (C=>XLXN_13, D=>XLXN_25, T=>XLXN_15, O=>XLXN_16);

XLXI_7 : FD port map (C=>XLXN_13, D=>XLXN_24, Q=>XLXN_15);

XLXI_10 : IFD_MXILINX_t4 port map (C=>XLXN_13, D=>XLXN_26, Q=>XLXN_24);

XLXI_11 : IFD_MXILINX_t4 port map (C=>XLXN_13, D=>XLXN_27, Q=>XLXN_25);

If you have equivalent_register_removal ON in XST it will do this, and override any "keep" attributes you place on the _t signal, giving obscure warning messages that aren't documented anywhere in the Answers Record.

You can locally apply an "equivalent_register_removal = FALSE" attribute to the tristate signal, to prevent the simplification. This worked here for the same problem.

- Brian