Xilinx ISE 7.1 to 9.2 Width Mismatch

I am getting 'width mismatch' warning on the char_slv assignement and text garbage after synthesis on this code that ran fine on ISE 7.1

Does any one have an idea of what's wrong?

Thanks much, Brad Smallridge AIVision

type text_type is array(0 to 2047) of character; constant text : text_type := " Bling 003 AiVision Pat. 5,768,421 " & . . . " " ;

signal char_slv : std_logic_vector(6 downto 0);

begin

text_proc: process(clk) variable char_val : character; variable char_pos : integer; begin if(clk'event and clk='1') then if(en='1') then char_val := text(to_integer(unsigned(text_index))); char_pos := character'pos(char_val); char_slv