Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?

Are you talking about differential signals? If so, most newer parts support differential I/O signals directly although many, if not most, might only be the lower voltage form, LVDS (which is usually what you want...but not always). In any case, this support is generally 'free' in that it is simply an I/O standard so there is no additional delay incurred in generating each half of the differential pair.

If you are talking about differential I/O, then you wouldn't explicitly write equations for each output, just the 'positive' half (which in the above case appears to be signal 'A'. You would then specify that 'A' is a differential pair and there would then be two physical pins assigned, one to each half.

Depending on the actual targetted part, there might be restrictions about just which pins can be differential and which can not and once you've picked the physical pin for the 'positive half' of the pair that also implicitly picks the pin for the 'negative half' as well.

Not sure what you mean, but maybe the answer is in what I've already posted.

Kevin Jennings

Hi Peter, Thank you for your answer. Your answer is good enough to meet my curiosity.

1. Interconnect has no inverter;
2. Any inverted signals will be absorbed by a LUT.

I very much appreciate Peter's EXCELLENT service for Xilinx company as an expert to answer all questions none of Xilinx clients can satisfactorily and authoritatively answers.

Weng

Not *all* inverters must be absorbed by LUTs. I'm worried you'll take this answer too far.

The SLICEs and IOBs both have a significant amount of control over inversions for input signals. If you open a design with FPGA Editor, you'll see many of the signals in the SLICE and IOB (even the BlockRAMs and Multipliers) such as clock, reset, the direct-input BX and BY values, and most of the signals *except* for the LUT inputs have a normal/invert option where the invert gets absorbed into the SLICE. The data and address into BlockRAMs and arguements of the multiply might not have automatic inversion available but their control signals mostly do.

The one condition I recall having to pay attention to the signal polarity in general logic - where it can affect timing - is when going in to a carry chain as a direct input to the MUXCY primitive. I can infer an add or subtract fine, but sometimes a needed inversion results in an extra LUT of delay before coming onto the carry chain because the .DI (or MULT_AND) inputs can't absorb the input. Often it's just a matter of producing an inverted form of the registers that feed the logic; this is sometimes referred to as "not gate push-back" if it's handled for you by the synthesizer.

- John_H

Hi John, Thank you for your advice. I am reading Virtex-5 CLB block diagram now. It is no doubt that the better the FPGA internal structure is understood, the high performance one can achieve.

Weng

I believe that particular "feature" has been addressed in the V5 carry chain structure so that now you have a LUT-like programmability in place of the former MULT_AND primitive on the MUXCY DI input. Yes, this particular thing has been the source of many not-so-obvious work-arounds to avoid having a non-absorbable inverter messing up the timing closure.