adding FPGA grounds

mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

It was recommended on some older xilinx CPLDs, but I think the general consensus is that it doesn't make much difference on modern BGA FPGAs

if if unused pins are connected to a plane it might help with cooling

The compiler should be smart enough to do what's best for unused pins.

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.

default is pulldown because it safe no matter what it is connected to, the tools don't know what you connect the pins to on the pcb

thermally disconnected ??

the tools doesn't know what the pins are connected to it has to pick something safe

If not electrically conductive, it's also less thermally conductive.

The drivers are likely deactivated, so it's doesn't matter where it's connected to.

I have seen some manufactures suggest this. I haven't measured it, but I would guess it could help, at least as long as the FPGA doesn't every try to drive the output high for a moment.

the thermal resistance of a mosfet depends on whether it on or off??

yes, when they are not activated it doesn't matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage

If the cell is activated, it creates heat by itself. I don't think it will conduct much heat from another cell, and that it will reduce much net heat. So, turning on a cell just for cooling doesn't make much sense.

For noise considerations, perhaps.

turning on the output doesn't matter but soldering the pin to a ground plane might

I'm sure it does, at some parts per million or billion. That would make a good grad thesis. Charge mobility and such.

We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that we want. One trick is to have an input pin influence a lot of logic. I can hardwire that pin high or low, but the compiler doesn't know that so it can't optimize my stuff away.

I bet you could build a state machine that winds to making a hard "1" to accomplish the same thing, but is complex enough that the compiler doesn't realize it.

rote:

landsniptechnology.com:

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o, probably not much difference.

d otherwise in the spec.

something safe

connected to.

keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage

I was just questioning the effectiveness of using additional cells for cool ing. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnections a re getting smaller, but the buffer cells need to be relatively bigger to ma intain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

ptechnology.com:

Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?

ably not much difference.

What does that have to do with cooling??? The pins are only connected to t he substrate which is not hard coupled thermally to the IC itself (it is ju st FR4 or something similar). So there won't be much thermal connection. On a flip chip this is entirely a different matter.

wise in the spec.

Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

Nothing. Cell to cell thermal transfer is not that important.

There are gold wires connecting the cells to pin/pad for electricity and thus heat.

Decide what's the best configuration when you don't tell it to use the pins/pads.

rote:

landsniptechnology.com:

FPGA

round

all such

grounds

least

eneral

FPGAs

ins.

o,

oling

o, probably not much difference.

d otherwise in the spec.

something safe

connected to.

keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage

The tools do not require there be an input for an output to be driven. If an input does not impact an output the logic it drives may be optimized out and so the input. Or if the logic will only ever drive a single value the logic can be optimized away. But it will never optimize away an output th at is driven in the HDL. That output will be driven by a fixed connection.

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ghlandsniptechnology.com:

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o keep them deactivated, it cannot assume unused pins are connected to grou nd and turn them on as extra grounds even if it would be an advantage

oling. Especially with output buffer cells, heat transfer to pin/pad is mu ch higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cell s as much as possible, but i doubt you can do any better than the compiler.

You are disputing an idea no one has suggested. As Lasse has said, the iss ue is not about the electrical connection and so not about "cells" on the c hip. The issue is the thermal connection between the board and the chip th rough the balls. Provide a hard thermal connection to the power plane to t he ball and you will get some additional cooling. Considering that the pad on the board can only be thermally connected to the power plane to a limit ed extent and the ball on the package only has a limited connection to the chip through the integrated PCB, this will not provide a large measure of t hermal relief. How effective this would be could be measured if no specs a re provided by the chip company.

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highlandsniptechnology.com:

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to keep them deactivated, it cannot assume unused pins are connected to gr ound and turn them on as extra grounds even if it would be an advantage

cooling. Especially with output buffer cells, heat transfer to pin/pad is m uch higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

The original suggestion was to compile it low and ground it for cooling, pe rhaps.

o not about "cells" on the chip. The issue is the thermal connection betwee n the board and the chip through the balls.

So is just adding more solder to the PCB pads, or making bigger pads.

will get some additional cooling.

That will only cool the cell you turn on for cooling, not much for other ce lls.

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probably not much difference.

Exactly.

thermally to the IC itself (it is just FR4 or something similar). So there won't be much thermal connection.

thus heat.

On a given thickness material, the resistivity gives an ohmic value of resi stance per "square" meaning a length equal to the width. Equate the round wire to the equivalent square wire and you will get a value of resistance t hat is not so low for a length equal to the width. Replace thermal units f or the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

therwise in the spec.

to in your HDL, nothing more, nothing less.

ns/pads.

If you don't tell it to electrically connect the unneeded pins and it will not connect the unneeded pins.

I'm sorry, but I have no idea what you think the "compiler" is going to do for you??? The tools synthesize what you tell them to synthesize. They do n't do your thinking for you. Using I/Os to provide electrical grounds is something you must tell the synthesis tool to do.

It is also useful to provide an equal number of power connections through t he I/Os since single ended CMOS I/Os use symmetrical voltage levels. The I /Os are just as sensitive to power bounce as they are ground bounce. When outputs pull high, they are drawing current through the power pins and the internal rail and output drives will drop. This will impact the switching threshold as much as ground bounce in CMOS.

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andsniptechnology.com:

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, probably not much difference.

d thermally to the IC itself (it is just FR4 or something similar). So ther e won't be much thermal connection.

d thus heat.

sistance per "square" meaning a length equal to the width. Equate the round wire to the equivalent square wire and you will get a value of resistance that is not so low for a length equal to the width. Replace thermal units f or the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

That thin gold wire is huge compared to the nm interconnecting fabric.

otherwise in the spec.

t to in your HDL, nothing more, nothing less.

pins/pads.

l not connect the unneeded pins.

o for you??? The tools synthesize what you tell them to synthesize. They do n't do your thinking for you. Using I/Os to provide electrical grounds is s omething you must tell the synthesis tool to do.

If you tell the compiler to ground the pin, it will just give you a logical ground. There is no special metal to ground it to the power rail. So, it better to just leave it off and save on power and heat.

.@highlandsniptechnology.com:

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r cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnectio ns are getting smaller, but the buffer cells need to be relatively bigger t o maintain the current capacity. If anything, you can try to space out cell s as much as possible, but i doubt you can do any better than the compiler.

perhaps.

I don't think anyone said that. The suggestion was simply "if unused pins are connected to a plane it might help with cooling"

so not about "cells" on the chip. The issue is the thermal connection betw een the board and the chip through the balls.

Again, you seem to not understand the nature of the issue. All pads have t he same solder balls. The pads on the PCB can be thermally connected to po wer planes that spread the heat across the board helping to lower the theta JA. It is hard to make pads any bigger. The issue is providing either a v ia in pad or a via with a WIDE dog bone (more of a football) to the adjacen t via or vias. In fact, if adjacent pins are picked, they can be "pooled" and connected to one another (as well as any pins on the same power rail) w ith all vias in the area connecting the common copper to the same power pla ne. This would provide the best cooling in aggregate. I guess you could c all this a "wide" pad.

ou will get some additional cooling.

cells.

It has NOTHING to do with "cells" or how they are electrically configured. NOTHING The balls are just connections between two PCBs. The chip is con nected to one PCB and traces and vias in that PCB connect the chip I/Os to the balls on the other side of that PCB which are then soldered to the PCB you design. No good thermal connection is made over the rather thin traces inside the BGA package. The heat is conducted through the substrate to th e balls.

BTW, some BGAs using bond wires and others use a flip chip which solders di rectly to the internal PCB. Take a look at this page with good illustratio ns.

hlandsniptechnology.com:

n FPGA

ground

all such

grounds

least

general

FPGAs

pins.

hought the board designer had to do that?

ooling

so, probably not much difference.

led thermally to the IC itself (it is just FR4 or something similar). So th ere won't be much thermal connection.

and thus heat.

resistance per "square" meaning a length equal to the width. Equate the rou nd wire to the equivalent square wire and you will get a value of resistanc e that is not so low for a length equal to the width. Replace thermal units for the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

The size of the transistors and chip features are totally irrelevant.

ed otherwise in the spec.

it to in your HDL, nothing more, nothing less.

e pins/pads.

ill not connect the unneeded pins.

do for you??? The tools synthesize what you tell them to synthesize. They don't do your thinking for you. Using I/Os to provide electrical grounds is something you must tell the synthesis tool to do.

al ground. There is no special metal to ground it to the power rail. So, it better to just leave it off and save on power and heat.

I think you don't understand how CMOS devices work. Please do some reading on the structure of a CMOS output. When a MOS transistor is turned on it provides an electrical connection between the drain and source. In this ca se one is connected to a power rail and the other to an output pin. That's a low(ish) impedance connection which is only different from a metal conne ction in terms of the impedance. But any connection is better than none. The "logic" is not at issue in any way.