Xilinx MIG and verifying UCF files


I just started to use the Xilinx Memory Interface Generator 1.72 and ran into some problems when veryfying the UCF file.

- Target xc4vfx100-ff1517

- DDR II SDRAM is MT47H64M16XX-37E

When doing "Verify my UCF" I always get the errors like ERROR: cntrl0_DDR2_A[0] (Address) is not supposed to be allocated in the bank 0

My UCF states NET "cntrl0_DDR2_A[0]" LOC = G25;

Looking at the Virtex-4 Packaging and Pinout Specification page 265 but states that G25 is indeed in bank 5.

Does anybody know what I could be doing wrong?

Thanks in advance!

Cheers, Simon

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Simon Heinzle
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