cfk,
Not "all", just one extra per Vcco power/ground pin pair is all that is required to reduce ground bounce by another 20% (roughly). The IO is set to a strong standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'. The pin is connected to the ground plane just like a ground pin. Adding pins past the first leads to a very small improvement (not worth it).
Making these grounds adjacent to clock inputs, or Vref pins can also aid in the reduction of user pcb crosstalk. The packages already have 3X spacing for every Vref, which means that x-talk coupling to/from Vref pins is 1/9 that of the coupling to any other pin in the package (ie, the package is not the 'problem').
Austin
cfk wrote:
And just to add a little spice to that broth, it was suggested one of the
> local Xilinx support folks on our last design to ground all the unused IOB
> pins and create more of a "virtual ground" (their term, not mine).
>
> > We will be designing with a large (xc2v6000) Virtex-II part in a ball-grid
> > array package that has maybe ~1000 balls, but we are using fairly few
> (~250)
> > "mission logic" I/O. Add in power & ground, configuration, etc., we will
> > have 100's of general-purpose I/O balls that are not needed.
> >
> > What should we do with them? Ground them? Let them float? If we can let
> them
> > float, do we even need a solder pad on the PWB for them to "land on"?
> >
> >