Re: 'Virtual Grounds'

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Austin Lesea Contact options for registered users 's Avatar (by Gravatar) posted on
August 4, 2003, 2:41 pm
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cfk,

Not "all", just one extra per Vcco power/ground pin pair is all that is required
to reduce ground bounce by another 20% (roughly).  The IO is set to a strong
standard (ie GTL, PCI, CMOS 24 mA, etc.) and set to a logic '0'.  The pin is
connected to the ground plane just like a ground pin.  Adding pins past the
first leads to a very small improvement (not worth it).

Making these grounds adjacent to clock inputs, or Vref pins can also aid in the
reduction of user pcb crosstalk.  The packages already have 3X spacing for every
Vref, which means that x-talk coupling to/from Vref pins is 1/9 that of the
coupling to any other pin in the package (ie, the package is not the 'problem').

Austin



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Hal Murray Contact options for registered users 's Avatar (by Gravatar) posted on
August 5, 2003, 3:51 am
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Re: 'Virtual Grounds'
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Does it do any good to use a similar setup for power?

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Austin Lesea Contact options for registered users 's Avatar (by Gravatar) posted on
August 5, 2003, 2:38 pm
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Re: 'Virtual Grounds'
Hal,

Vcc bounce is hardly an issue with most designs.  That is why it is not often
considered.

Ground bounce affects everything:  slicing level, jitter, timing, function of the
device (etc).

Vcc bounce my affect IO output timing, jitter, but is generally a second order
effect.

You can use "virtual Vcco" pins as well, but it is rare that it is done (and
ends up
being useful).

Austin

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Hal Murray Contact options for registered users 's Avatar (by Gravatar) posted on
August 6, 2003, 6:22 am
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Re: 'Virtual Grounds'
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Thanks.

Why the asymmetry?

I'd expect TTL type inputs (referenced to 2 diodes above ground) to be
sensitive to ground bounce only, but what about others?

I thought the reference for CMOS was roughly 1/2 way between Vcc and
Ground.  Wouldn't that wiggle if Vcc wiggled?

Is PECL referenced to Vcc?

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Jim Granville Contact options for registered users 's Avatar (by Gravatar) posted on
August 6, 2003, 7:09 am
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Re: 'Virtual Grounds'
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 Yes. What separates the issue on FPGA and bigger CPLD, is the core Vcc
is
not the same pins as Vcc[io] - whilst bounce on the common GND can
disturb the
core (where it is certainly noticed :)
 Vcc[io] bounce WILL disturb the IO threshold, but most digital signals
pass thru the threshold very quickly.
 In a jitter paranoid application, you could expect to notice Vcc
related
crosstalk.
 
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Outputs are emitter followers on open collectors, so yes.
PECL is normally differential, so you get PSR that way, plus you
also reduce any spikes, due to the balance drive.

- jg

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