Xilinx OPB custom interface

I created a custom opb component using the create peripheral wizard. Im using the IP2BUSxferAck to provide a 4 wait states for reads and writes. During reads, the CS pulse created by the OPB component is about extended as it should be. The problems is during writes... the CS pulse short as if NO wait states are beign added. Except for bringing out the required signals (address, ack, data), no changes where made to the vhdl file generated by the wizard.

Rich

Reply to
Richad Klosinski
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Richard,

Are you inhibiting posted writes? From what you've described, it seems to me that the IPIF is configured for posted writes. There is a signal on the IPIC (IP2Bus_PostedWrInh) which inhibits posted writes, thereby requiring a full handshake transfer for writes.

Matt

Richad Klos> I created a custom opb component using the create peripheral wizard.

Reply to
Matthew Ouellette

Hi Rich,

The OPB slave template generated by Create Peripheral Wizard assumes posted write transactions by default. If you want to implement acknowledged write transactions, you'll need to assert the IP2Bus_PostedWrInh (posted write inhibit). See opb_ipif_v3_01_a datasheet for detail explaination.

thanks, y> I created a custom opb component using the create peripheral wizard.

Reply to
Yong Zhu

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