I created a custom opb component using the create peripheral wizard. Im using the IP2BUSxferAck to provide a 4 wait states for reads and writes. During reads, the CS pulse created by the OPB component is about extended as it should be. The problems is during writes... the CS pulse short as if NO wait states are beign added. Except for bringing out the required signals (address, ack, data), no changes where made to the vhdl file generated by the wizard.