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getting back Xilinx ISE commands

Hi all,

I am using Webpack ISE to do PAR for Coolrunner.

How to get back all command line from VHDL and UCF parser to JEDEC generation (parser, synthesis and par works)

The goal is to do a generic project (using webpack IDE interface) and to get back all ISE command line, and to re-run the ISE command line for an other VHDL file with minor changes. All the work would be via script for generating about 50 news configs of our Chameleon POD.

Are there any command log files?

Thanks for all advices, Regards, Laurent Gauch

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Reply to
Amontec Team, Laurent Gauch
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Have a look at the chapter about "xflow" in the ISE Documentation. That's the command-line-tool to do the complete flow from synthesis to bitfile generation (I assume you can generate JEDEC-files as well). The options for each of the steps are set in *.opt-files, that reside in $XILINX/epld/data. You can copy those and modify the local copies, and run "xflow" with these instead of the globally available ones.

"xflow" is really not that complicated, and is great for using inside scripts, so that should be what you need.

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42]  [durkinsn , fraunhofer])
Reply to
Sean Durkin

Sean,

I will try the xflow way. many thanks Laurent

Reply to
Amontec Team, Laurent Gauch

Hi,

I need to know where I have to include my .ucf file in XFLOW!

Laurent

Sean Durk> Am>

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Reply to
Amontec Team, Laurent Gauch

As long as it has the same name as the rest of the design XFLOW should find it automatically. E.g., if you have a "top.vhd", or a "top.ngc", then XFLOW should find a "top.ucf" on it's own, if it resides in the current directory. Otherwise you can change it in the *.opt-file for the "implement" stage (fast_runtime.opt, for example, or whatever you use).

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42]  [durkinsn , fraunhofer])
Reply to
Sean Durkin

------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow!

---- See

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Reply to
Amontec Team, Laurent Gauch

For verilog and FPGA the log file is .cmd_log just run the flow once and copy it to a *.bat file

from the command line it pretty easy to guess what files you need to look at to set options etc. and they are quite easy to read and modify

-Lasse

Reply to
Lasse Langwadt Christensen

All are working fine. I am now able to pass from VHDL source files to SVF output files only using script ! We have now a Chameleon POD self programmable from VHDL source. (Just need to intall the Free webpack) :-)

A very nice solution.

Laurent www.am> Am>

Reply to
Amontec Team, Laurent Gauch

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